Manuale d’uso / di manutenzione del prodotto S3C2440A del fabbricante Samsung
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S3C2440A 32-BIT RISC MICROPROCESSOR USER'S MANUAL PRELIMINA RY Rev isio n 0.14 (June 30, 2004).
S3C2440A RISC MICROPROCESSO R PRODUCT OVERVIEW 1-1 1 PRODUCT OVERVIEW INTRODUCTION This user’s m anual describes SAMSUNG 's S3C2440A 16/32-bit RISC m ic roproces sor. SAMSUNG’s S3C2440A is designed to provide hand-held devic es and general applic ations with low-power, and high-perform ance m icro- controller s olution in sm all die size.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-2 FEA TURES A rchit ecture • Integrated system f or hand-held devic es and general em bedded applications. • 16/32-Bit RISC architec ture and powerful instruction s et with ARM920T CPU core. • Enhanced ARM architec ture MMU to support W inCE, EPOC 32 and Linux.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-3 FEA TURES (Continued) Interrupt Controller • 60 Interrupt sour ces (One W atch dog tim er, 5 tim ers , 9 UARTs, 24 external interrupts , 4 DMA, 2 RT.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-4 FEA TURES (Continued) A /D Converter & Touch Screen Inter face • 8-ch m ultiplexed AD C • Max.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-5 BLOCK DIA GRAM A RM920T ARM 9 T D M I Processo r core (Inte rnal E mbedded ICE) DD[31:0 ] Writ eBack PA Tag RA M Data MMU C13 DVA[31:0] DVA[31:0] Inst.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-6 PIN A SSIGNMENTS BOTTOM VIEW U T R P N M L K J H G F E D C B A 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 Figure 1-2.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-7 Table 1- 1. 289-Pin FBG A Pin Assignments – Pin Numb er Order (Sheet 1 o f 3) Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name A1 VDDi C1.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-8 Table 1- 1. 289-Pin FBG A Pin Assignments – Pin Numb er Order (Sheet 2 o f 3) Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name G1 VSSOP J.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-9 Table 1- 1. 289-Pin FBG A Pin Assignments – Pin Numb er Order (Sheet 3 o f 3) Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name N1 VSSOP R.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-10 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 1 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O Sta.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-11 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 2 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O Sta.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-12 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 3 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O Sta.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-13 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 4 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O Sta.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-14 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 5 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O Sta.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-15 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 6 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O Sta.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-16 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 7 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O Sta.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-17 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 8 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O Sta.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-18 Table 1- 2. S3C2440A 289- Pin FBGA Pin A ssignmen ts (Sheet 9 o f 9) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @Sleep I/O Sta.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-19 NOTE: 1. The @BUS REQ. shows the pin state at the ex ternal bus, which is used by the other bus master. 2. ' – ‘ mark indicates the unchanged pin state at Bus Request mode. 3. Hi-z or Pre means Hi-z or early state and it is determined by the setting of MISCCR register.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-20 THE T ABLE BELOW SHOWS I/O TY PES A ND DESCRIPT IONS. Input (I)/Output (O) Type Descriptions d12i(vdd12ih) 1.2V Vdd for alive power d12c(vdd12ih_cor e), si(vss ih) 1.2V Vdd/Vss for inter nal logic d33o(vdd33oph), so( vssoph) 3.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-21 SIGNAL DESCRIPTIONS Table 1- 3. S3C2440A Sign al Descriptions ( Sheet 1 of 6) Signal Input/Output Descriptions Bus Contro ller OM[1:0] I OM[1:0] sets S3C2440A in the T EST m ode, which is used only at fabrication.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-22 Table 1- 3. S3C2440A Sign al Descriptions ( Sheet 2 of 6) Signal Input/Output Descriptions LCD Control Unit VD[23:0] O STN /TFT/ SEC TFT: LCD Data Bu.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-23 Table 1- 3. S3C2440A Sign al Descriptions ( Sheet 3 of 6) Signal Input/Output Descriptions UA RT RxD[2:0] I UART rec eives data input TxD[2:0] O UART.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-24 Table 1- 3. S3C2440A Sign al Descriptions ( Sheet 4 of 6) Signal Input/Output Description SPI SPIMISO[1:0] IO SPIMISO is the m aster data input line, when SPI is c onfigured as a mas ter. W hen SPI is conf igured as a slave, thes e pins revers e its role.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-25 Table 1- 3. S3C2440A Sign al Descriptions ( Sheet 5 of 6) Signal Input/Output Description Reset, Clock & Pow er XT Opll AO Cry s tal Output for internal osc circuit. W hen OM[3:2] = 00b, XT Ipll is used f or MPLL CLK sour ce and UPLL CLK source.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-26 Table 1- 3. S3C2440A Sign al Descriptions ( Sheet 6 of 6) Signal Input/Output Description Pow er VDDalive P S3C2440A reset block and port status register VDD. It should be alway s supplied whether in norm al m ode or in Sleep m ode.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-27 S3C2440A SPECIAL REGISTERS Table 1- 4. S3C2440A Sp ecial Registers (Sheet 1 of 14) Register Name A dd ress (B.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-28 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 2 of 14) Register Name A dd ress (B. Endian) A ddress (L.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-29 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 3 of 14) Register Name A dd ress (B. Endian) A ddress (L.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-30 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 4 of 14) Register Name A dd ress (B. Endian) A ddress (L.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-31 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 5 of 14) Register Name A dd ress (B. Endian) A ddress (L.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-32 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 6 of 14) Register Name A ddress (B. Endian) Address (L.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-33 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 7 of 14) Register Name A ddress (B. Endian) Address (L.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-34 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 8 of 14) Register Name A ddress (B. Endian) Address (L.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-35 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 9 of 14) Register Name A dd ress (B. Endian) Address (L.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-36 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 10 of 14) Register Name A dd ress (B. Endian) Address (L.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-37 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 11 of 14) Register Name A d dress (B. Endian) A dd ress (L.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-38 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 12 of 14) Register Name A d dress (B. Endian) Address (L.
S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW 1-39 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 13 of 14) Register Name Address (B. Endian) Address (L.
PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR 1-40 Table 1- 4. S3C2440A Sp ecial Registers (Sheet 14 of 14) Register Name Address (B. Endian) Address (L.
S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-1 2 PROGRA MMER'S MODEL OVERVIEW S3C2440A is developed using the advanced ARM920T cor e, which has been designed by Advanced RISC Machines, Ltd.
PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-2 BIG-ENDIA N FORM A T In Big-Endian for mat, the m os t significant byte of a word is stor ed at the lowest number ed by te and the leas t significant byte at the highest num bered byte. By te 0 of the m em ory sy stem is therefor e connected to data lines 31 through 24.
S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-3 OPERA TING MO DES ARM920T s upports seven m odes of operation: • User (usr): T he norm al ARM progr am ex ecution state • FIQ (fiq): Design.
PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-4 R0 R1 R2 R3 R4 R5 R6 R7 R9 R8 R10 R11 R12 R13 R14 R15 (PC) R0 R1 R2 R3 R4 R5 R6 R7 R9 R8 R10 R11 R12 R13_ svc R14_ svc R15 (PC) R0 R1 R2 R3 R4 .
S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-5 The T HUM B State Regist er Set The THUMB state regis ter set is a s ubset of the ARM s tate set. T he program m er has direc t acces s to eight general register s, R0-R7, as well as the Program Counter (PC), a stack pointer regis ter (SP), a link r egister (LR), and the CPSR.
PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-6 The relat ionship b etween A RM and THUM B state reg isters The relations hip between ARM and THUMB state r egisters ar e as below:- • THUMB .
S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-7 A ccessing Hi-Registers in T HUM B State In THUMB st ate, registers R8-R15 (“Hi regi sters”) are not par t of the standar d register s et. However, the assem bly language programm er has lim ited access to them , and can use them for fast tem por ary storage.
PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-8 The Condition Code Flags The N, Z, C and V bits are the condition c ode flags. T hese m ay be changed as a result of arithm etic and logical operations, and m ay be tested to determine whether an instr uction should be ex ecuted.
S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-9 Table 2- 1. PSR Mo de Bit Values M[ 4:0] M ode Visible T HUM B state regist ers Visible A R M st ate registers 10000 User R7..R0, LR, SP PC, CPSR R14..R0, PC, CPSR 10001 FIQ R7..R0, LR_fiq, SP_f iq PC, CPSR, SPSR_fiq R7.
PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-10 EXCEPTIO NS Exceptions ar ise whenever the norm al flow of a program has to be halted tem porarily, for exam ple to s ervice an interrupt f rom a peripheral.
S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-11 Exception Entry/Exit Summary Table 2-2 s um mar izes the PC value preserved in the relevant R14 on ex ception entry, and the recom mended instruc tion for ex iting the exception handler. Tabl e 2-2.
PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-12 IRQ The IRQ (Interrupt Request) exception is a norm al inter rupt caused by a LOW level on the nIRQ input.
S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-13 Software Interr upt The Sof tware Interrupt Inst ruction (SW I) is used for entering Supervisor m ode, usually to request a particular supervisor function.
PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-14 Exception Priorities W hen multiple ex ceptions aris e at the sam e tim e, a fixed pr iority system determ ines the or der in which they are handled: Highest priority : 1. Reset 2. Data abor t 3.
S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL 2-15 INTERRUPT LA T ENCIES The worst c ase latency for FIQ, as sum ing that it is enabled, cons ists of the longest tim e the request c an take to .
PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR 2-16 NOTES.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-1 3 A RM INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter desc ribes the ARM instr uction set in the ARM920T core.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-2 NOT ES Some ins truction c odes are not def ined but does not cause Undef ined instruc tion trap to be tak en, for instance a m ultiply instruction with bit 6 changed to a 1. Thes e instruc tions should not be us ed, as their action m ay change in future ARM im plem entations.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-3 Table 3-1. The A RM Instruction Set (Continued) Mnemonic Instruction A ction MRC Move from coproc essor r egister to CPU register Rn: = cRn {<op.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-4 THE CONDITION FIELD In ARM state, all instr uctions are c onditionally executed acc ording to the state of the CPSR condition codes and the instruct ion's condition f ield. This f ield (bits 31:28) determ ines the circ ums tances under which an instruction is to be executed.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-5 BRA NCH AND EXCHA NGE (BX) This instruct ion is only executed if the condition is true. The var ious conditions ar e defined in T able 3-2. This instruction per form s a br anch by copy ing the contents of a general r egister, Rn, into the Progr am Counter , PC.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-6 Examples A DR R0, Into_T HUMB + 1 G enerate branch target addr ess and set bit 0 high – hence it com es in T HUMB state BX R0 Branch and change to T HUMB state.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-7 BRA NCH AND BRA NCH W ITH LINK (B, BL) The ins truction is only executed if the condition is true. T he various c onditions are def ined Table 3- 2. The instruc tion encoding is shown in Figure 3- 3, below.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-8 A SSEM BLER SY NTAX Items in “{}” ar e optional. Items in “<>” m us t be present. B{L}{cond} <expression> {L} Used to request the Br anch with Link f orm of the instr uction. If absent, R14 will not be af fected by the instruction.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-9 DA TA PROCESSING The data proc essing ins truction is only executed if the condition is true. T he conditions are defined in T able 3-2.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-10 The ins truction produc es a res ult by per form ing a spec ified arithm etic or logical operation on one or two operands.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-11 CPSR FLAGS The data proc essing operations can be clas sified as logic al or arithm etic. T he logical operations (AND, EOR, T ST, TEQ, O RR, MOV, BIC, MVN) perf orm the logical action on all c orresponding bits of the operand or operands to produce the res ult.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-12 SHIFTS W hen the second operand is specif ied to be a shifted r egister, the oper ation of the barrel s hifter is controlled by the Shift f ield in the instruction. T his f ield indicates the type of shif t to be perfor med ( logical left or right, arithm etic right or rotate right).
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-13 31 Contents of Rm Value of Operand 2 0 carry out 4 5 0 0 0 0 0 Figure 3-7. Logica l Shift Right The f orm of the s hift field which m ight be expec ted to corres pond to LSR #0 is used to encode LSR #32, which has a zero result with bit 31 of Rm as the carr y output.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-14 Rotate right (ROR) operations reus e the bits which "overs hoot" in a logical shif t right operation by reintroducing them at the high end of the result, in plac e of the zeros us ed to fill the high end in logical r ight operations.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-15 Register Spec ified Shift Amount Only the least significant byte of the contents of Rs is used to determ ine the shif t am ount.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-16 IMM EDIATE OPERA ND ROTA T ES The im m ediate operand rotate f ield is a 4 bit unsigned integer which specif ies a shif t operation on the 8 bit imm ediate value. T his value is zero extended to 32 bits, and then subjec t to a rotate right by tw ice the value in the rotate field.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-17 A SSEM BLER SY NTAX • • • • MOV,MVN (single oper and instruc tions). <opcode>{cond} {S} Rd,<Op2> • • • • CMP,CMN,T EQ,TST (instruc tions which do not produce a r esult).
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-18 PSR TRA NSFER (MR S, MSR) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-19 MSR (transfer register contents or immediate value to PSR flag bits only) Cond Source operand Pd 101001111 31 22 27 28 11 12 21 23 I1 0 00 26 25 2.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-20 RESERVED BITS Only tw elve bits of the PSR are def ined in ARM920T ( N,Z,C,V,I,F, T & M[4:0]) ; the rem aining bits are res erved for use in futur e versions of the proces sor. Ref er to Figure 2-6 f or a f ull description of the PSR bits.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-21 A SSEM BLY SYNT A X • • • • MRS - transf er PSR contents to a register MRS{cond} Rd,<ps r> • • • • MSR - trans fer regis ter.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-22 MULTIPLY A ND MULTIP LY-A CCUMULATE (MUL, MLA ) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figur e 3-12.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-23 If the Op erands Are Interpreted as Signed Operand A has the value - 10, operand B has the value 20, and the res ult is -200 which is correc tly represented as 0xFFFFFF38.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-24 CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. T he N (Negative) and Z (Zero) flags are s et corr ectly on the result (N is m ade equal to bit 31 of the r esult, and Z is s et if and only if the result is zero).
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-25 MULTIPLY LONG A ND MULTIP LY-ACCUMULA TE LONG (MULL, MLA L) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figur e 3-13.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-26 OPERA ND REST RICTIONS • R15 mus t not be used as an operand or as a destination regis ter. • RdHi, RdLo, and Rm m us t all specif y dif fer ent registers . CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-27 A SSEM BLER SY NTAX Table 3- 5. A ssemb ler Syntax Descriptions Mn emonic Descripti on Purpose UMULL{cond}{S} RdLo,RdHi,Rm,Rs Uns igned Multiply L.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-28 SINGLE DA TA TRANSFER (LDR, STR) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figur e 3-14.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-29 OFFSET S A ND A UT O-INDEXING The of fset f rom the base m ay be either a 12 bit unsigned binary imm ediate value in the instruc tion, or a second register ( possibly shifted in som e way ). The of fs et m ay be added to ( U=1) or subtr acted fr om (U=0) the base register Rn.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-30 LDR from word aligned address A+3 A A+2 A+1 memory 24 16 8 0 A B C D register 24 16 8 0 A B C D LDR from address offset by 2 A+3 A A+2 A+1 memory 24 16 8 0 A B C D register 24 16 8 0 A B C D Figure 3-15.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-31 USE OF R15 W rite-back m ust not be spec ified if R15 is spec ified as the bas e register ( Rn). W hile using R15 as the bas e register, you mus t rem ember it contains an addres s of 8 by tes on from the addres s of the c urrent instr uction.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-32 A SSEM BLER SY NTAX <LDR| STR>{cond}{B}{T} Rd,<Address> where: LDR Load fr om mem ory into a register STR Store f rom a regis ter into m em ory {cond} Two-charac ter condition m nem onic.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-33 EXA M PL ES STR R1,[R2,R4]! ; Store R1 at R2+R4 ( both of which are regis ters) ; and write bac k addr ess to R2. ST R R1,[R2],R4 ; Store R1 at R2 and write back R2+R4 to R2. LDR R1,[R2,#16] ; Load R1 from contents of R2+16, but don't write back.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-34 HA LFWORD AND SIGNED DA TA TRANSFER (LDRH/STRH/LDRSB/LDRSH) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figur e 3-16.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-35 31 27 19 15 Cond 28 16 11 12 21 23 1 20 LR n R d [3:0] Immediate Offset (Low Nibble) [6][5] S H 0 0 = SWP instruction 0 1 = Unsigned halfword 1 1 .
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-36 HA LFWORD LOAD A ND STORES Setting S=0 and H=1 may be used to transf er unsigned Half -words between an ARM920T r egister and m em ory. The ac tion of LDRH and ST RH instructions is influenced by the BIGEND control signal.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-37 Big-Endian Configuration A signed byte load (LDRSB) expects data on data bus inputs 31 through to 24 if the s upplied address is on a word boundary, on data bus inputs 23 through to 16 if it is a word addr ess plus one byte, and so on.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-38 A SSEM BLER SY NTAX <LDR|STR>{cond}<H|SH|SB> Rd,<address> LDR Load fr om mem ory into a register STR Store f rom a regis ter into m em ory {cond} Two-charac ter condition m nem onic.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-39 EXA M PL ES LDRH R1,[R2,-R3]! ; Load R1 from the c ontents of the half word address ; c ontained in R2-R3 (both of which are regist ers) ; and write bac k addr ess to R2 ST RH R3,[R4,#14] ; Store the halfword in R3 at R14+14 but don't write back .
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-40 BLOCK DA TA TRA NSFE R (LDM, STM) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figur e 3-18 .
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-41 A DDRESSING MO DES The trans fer addr esses ar e determ ined by the c ontents of the bas e register ( Rn), the pre/post bit ( P) and the up/ down bit (U). T he registers are transf erred in the order lowest to highest, so R15 ( if in the list) will always be transf erred last.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-42 Rn 1 R1 R1 2 R5 3 R1 R5 4 R7 Rn 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Figure 3-20. Pre- Increment Addressing Rn 1 R1 R1 2 R5 3 R1 R5 4 R7 Rn 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Figure 3-21.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-43 Rn 1 R1 R1 2 R5 3 R1 R5 4 R7 Rn 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Figure 3-22.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-44 INCLUSION OF T HE BASE IN THE REGIST ER LIST W hen write-back is specif ied, the base is written back at the end of the second c ycle of the instruction. Dur ing a STM, the f irst regis ter is written out at the star t of the sec ond cycle.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-45 A SSEM BLER SY NTAX <LDM|STM>{cond} <FD|ED| F A|EA| IA|IB|DA|DB> Rn{!},<Rlis t>{^} where: {cond} Two charac ter condition m nem onic.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-46 EXA M PL ES LDMFD SP! ,{R0,R1,R2} ; Unstack 3 r egisters. ST MIA R0,{R0-R15} ; Save all registers. LDMFD SP!,{ R15} ; R15 ← (SP), CPSR unc hanged. LDMFD SP!,{ R15}^ ; R15 ← (SP), CPSR <- SPSR_mode ; ( allowed only in pr ivileged modes ).
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-47 SINGLE DATA SW A P (S W P) 31 19 15 Cond 28 16 11 12 21 23 B 20 00 Rn Rd [3:0] Source Register [15:12] Destination Register [19:16] Base Register [22] Byte/Word Bit 0 = Swap word quantity 1 = Swap word quantity [31:28] Condition Field 22 00010 0000 Rm 1001 2 7 87 43 0 Figure 3-23.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-48 USE OF R15 Do not use R15 as an operand ( Rd, Rn or Rs) in a SW P ins truction. DA TA A BORTS If the addres s used f or the swap is unacc eptable to a mem ory managem ent system , the mem or y m anager c an flag the problem by driving ABORT HIGH .
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-49 SOFTWARE INTERRUPT (SWI) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-50 A SSEM BLER SY NTAX SW I{cond} <ex pression> {cond} Two charac ter condition m nem onic, T able 3-2. <express ion> Evaluated and placed in the c om ment f ield (which is ignor ed by ARM920T ).
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-51 COPROCESSOR D A TA OPERA TIONS (CD P) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figur e 3-25.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-52 INSTRUCT ION CYCLE T IMES Coprocess or data operations tak e 1S + bI incr emental c y cles to execute, where b is the num ber of c y c les spent in the coproces sor busy-wait loop. S and I are defined as sequential (S-c y c le) and internal ( I-cycle).
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-53 COPROCESSOR DA TA TR ANSFER S (LDC, STC) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figure 3- 26.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-54 THE CO PROCESSOR FI ELDS The CP# f ield is used to identif y the coproces sor which is required to supply or accept the data, and a copr ocessor will only res pond if its num ber matc hes the contents of this f ield.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-55 A SSEM BLER SY NTAX <LDC|STC>{cond}{ L} p#,cd,<Addres s> LDC Load fr om mem ory to coprocess or STC Store f rom coproces sor to m em ory {L} W hen present perf orm long transf er (N=1) , otherwise perfor m s hort transf er (N=0) {cond} Two charac ter condition m nem onic.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-56 COPROCESSOR REG ISTER T RANSFERS (MRC, M CR) The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion encoding is shown in Figur e 3-27.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-57 TRANSFERS TO R15 W hen a coproces sor register transf er to ARM920T has R15 as the destination, bits 31, 30, 29 and 28 of the transf erred word are copied into the N, Z , C and V flags res pectively.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-58 UNDEFINED INSTRUCT ION The ins truction is only executed if the condition is true. T he various c onditions are def ined in Table 3- 2. The instruc tion form at is s hown in Figure 3-28. 31 27 Cond 28 25 24 011 xxxxxxxxxxxxxxxxxxxx 1 xxxx 543 0 Figure 3-28.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-59 INSTRUCT ION SET EXAMPLES The f ollowing examples show way s in which the basic ARM920T instruc tions can c om bine to give effic ient code. None of these m ethods saves a great deal of execution tim e (although they may save som e), m ostly they jus t save code.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-60 Division and Remainder A number of divide routines for s pecif ic applications ar e provided in sourc e form as part of the ANSI C libr ary provided with the ARM Cross Developm ent T oolkit, available f rom your supplier.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-61 5. Overf low in unsigned multiply accum ulate with a 64 bit result UMULL Rl,Rh,Rm,Rn ; 3 to 6 cy c les ADDS Rl,Rl,Ra1 ; Lower accum ulate ADC Rh,Rh,Ra2 ; Upper ac cum ulate BCS overflow ; 1 c y cle and 2 register s 6.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-62 Multiplication by 6 ADD Ra,Ra,Ra,LSL #1 ; Multiply by 3 MOV Ra,Ra,LSL#1 ; and then by 2 Multiply by 10 and add in extra num ber ADD Ra,Ra,Ra,LSL#2 ; Multiply by 5 ADD Ra,Rc,Ra,LSL#1 ; Multiply by 2 and add in next digit General rec ursive m ethod for Rb := Ra*C, C a constant: 1.
S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET 3-63 LOA DING A WORD FROM A N UNKNOW N A LIGNM ENT ; Enter with address in Ra (32 bits) uses ; Rb, Rc result in Rd.
ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 3-64 NOTES.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-1 4 THUMB INSTRUCTION SET THUMB INSTRUCTION SET FORMAT The thum b instruction sets are 16-bit versions of ARM ins truction sets (32-bit f orm at). T he ARM instruc tions are reduced to 16-bit ver sions.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-2 FORMAT SUMM ARY The T HUMB instruc tion set f orm ats are shown in the f ollowing figure. Move Shifted register 0 0 0 000 000 000 1 0 0 010 0 0 0.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-3 OPCODE SUMM ARY The following table summ arizes the THUMB inst ruction set. F or fur ther infor m ation about a particular ins truction please ref er to the sections listed in the right-m os t colum n.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-4 Table 4-1. THUM B Instruction Set Opc odes (Continued) Mn emonic Instru ction Lo-Register Operand Hi-Register Operand Condition Codes Set NEG Neg.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-5 FORMA T 1: MOV E SHIFTED REGISTER 15 0 0 14 10 [2:0] Destination Register [5:3] Source Register [10:6] Immediate Vale [12:11] Opcode 0 = LSL 1 = LSR 2 = ASR Offset5 65 32 Rd 00 13 12 11 Op Rs Figure 4-2.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-6 INSTRUCT ION CYCLE T IMES All instructions in this for m at have an equivalent ARM instruc tion as shown in T able 4-2. The ins truction c ycle times for the THUMB inst ruction are identic al to that of the equivalent ARM instr uction.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-7 FORMA T 2: A DD/SUBTRACT 15 0 14 10 [2:0] Destination Register [5:3] Source Register [8:6] Register/Immediate Vale [9] Opcode 0 = ADD 1 = SUB [10] Immediate Flag 0 = Register operand 1 = Immediate oerand Rn/Offset3 Rd 00 13 12 11 Op Rs 98 111 65 32 0 Figure 4-3.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-8 INSTRUCT ION CYCLE T IMES All instructions in this for m at have an equivalent ARM instruc tion as shown in T able 4-3. The ins truction c ycle times for the T HUMB instr uction are identic al to that of the equivalent ARM instr uction.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-9 FORMA T 3: MOVE/COMPARE/A DD/SUBTRA CT IMME DIATE 15 0 0 14 10 [7:0] Immediate Vale [10:8] Source/Destination Register [12:11] Opcode 0 = MOV 1 = CMP 2 = ADD 3 = SUB Offset8 Rd 00 13 12 11 Op 7 8 Figure 4-4.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-10 INSTRUCT ION CYCLE T IMES All instructions in this for m at have an equivalent ARM instruc tion as shown in T able 4-4. The ins truction c ycle times for the THUMB inst ruction are identic al to that of the equivalent ARM instr uction.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-11 F O R M AT 4 : AL U O P E R AT I O N S 15 0 0 14 10 [2:0] Source/Destination Register [5:3] Source Register 2 [9:6] Opcode 5 6 3 Rd 00 13 12 11 Op Rs 0 00 9 2 Figure 4-5. For mat 4 OPERA T ION The f ollowing instructions perform ALU oper ations on a Lo register pair.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-12 INSTRUCT ION CYCLE T IMES All instructions in this for m at have an equivalent ARM instruc tion as shown in T able 4-5. The ins truction c ycle times for the THUMB inst ruction are identic al to that of the equivalent ARM instr uction.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-13 FORMA T 5: HI-REGISTER OPERATIONS/BRA NCH EXCHANGE 15 0 0 14 10 [2:0] Destination Register [5:3] Source Register [6] Hi Operand Flag 2 [7] Hi Operand Flag 1 [9:8] Opcode 65 32 Rd/Hd 00 13 12 11 Op Rs/Hs 0 00 9 8 7 H1 H2 Figure 4-6.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-14 Table 4-6. Summary of Format 5 Instructions (Continued) Op H1 H2 THUMB assemb ler ARM equiv alent Description 01 1 1 CMP Hd, Hs CMP Hd, Hs Compar e two registers in the range 8-15. Set the condition code f lags on the result.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-15 EXA M PL ES Hi-Register Operations ADD PC, R5 ; PC := PC + R5 but don't set the condition codes . CMP R4, R12 ; Set the condition codes on the result of R4 - R12. MOV R15, R14 ; Move R14 (LR) into R15 (PC) but don't set the condition codes , eg.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-16 FORMA T 6: PC-RELA TIVE LOA D 15 0 0 14 10 [7:0] Immediate Value [10:8] Destination Register Word 8 00 13 12 11 Rd 0 0 87 Figure 4-7. For mat 6 OPERA T ION This instruction loads a word fr om an addr ess s pecified as a 10-bit im m ediate off set fr om the PC.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-17 INSTRUCT ION CYCLE T IMES All instruc tions in this f orm at have an equivalent ARM instr uction. T he instruc tion cy c le times for the THUMB instruc tion are identical to that of the equivalent ARM instruct ion.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-18 FORMA T 7: LOAD /STORE WITH REGISTER OFFSET [2:0] Source/Destination Register [5:3] Base Register [8:6] Offset Register [10] Byte/Word Flag 0 = .
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-19 OPERA T ION Thes e instructions transf er byte or word values between registers and m em ory. Memory addresses are pre- indexed using an of fset r egister in the range 0- 7. The T HUMB assem bler syntax is shown in Table 4-8.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-20 FORMA T 8: LOA D/STORE S IGN-E X TENDED BYTE/HALFWORD [2:0] Destination Register [5:3] Base Register [8:6] Offset Register [10] Sign-Extended Flag 0 = Operand not sing-extended 1 = Operand sing-extended [11] H Flag 15 0 0 14 10 65 32 Rd 10 13 12 11 Rb 1 HS 98 Ro 1 Figure 4-9.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-21 INSTRUCT ION CYCLE T IMES All instructions in this for m at have an equivalent ARM instruc tion as shown in T able 4-9. The ins truction c ycle times for the THUMB inst ruction are identic al to that of the equivalent ARM instr uction.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-22 FORMA T 9: LOAD /STORE WITH IMMEDIA TE OFFSET [2:0] Source/Destination Register [5:3] Base Register [10:6] Offset Register [11] Load/Store Flag .
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-23 OPERA T ION Thes e instructions transf er byte or word values between registers and m em ory using an imm ediate 5 or 7-bit off set. The T HUMB ass em bler syntax is shown in Table 4-10. Table 4- 10.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-24 FORMA T 10: LOAD/STORE HA LFW ORD [2:0] Source/Destination Register [5:3] Base Register [10:6] Immediate Value [11] Load/Store Flag 0 = Store to memory 1 = Load from memory 15 0 0 14 10 65 32 Rd 10 13 12 11 Rb 0 L Offset5 Figure 4-11.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-25 INSTRUCT ION CYCLE T IMES All instruc tions in this f orm at have an equivalent ARM instr uction as s hown in Table 4-11. T he ins truction cycle times for the THUMB inst ruction are identic al to that of the equivalent ARM instr uction.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-26 FORMA T 11: SP-RELATIVE LOA D/STORE [7:0] Immediate Value [10:8] Destination Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory 15 0 1 14 10 00 13 12 11 Word 8 1 L Rd 7 8 Figure 4-12.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-27 INSTRUCT ION CYCLE T IMES All instruc tions in this f orm at have an equivalent ARM instr uction as s hown in Table 4-12. T he ins truction cycle times for the THUMB inst ruction are identic al to that of the equivalent ARM instr uction.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-28 FORMA T 12: LOA D A DDRESS [7:0] 8-bit Unsigned Constant [10:8] Destination Register [11] Source 0 = PC 1 = SP 15 0 1 14 10 01 13 12 11 Word 8 0 SP Rd 7 8 Figure 4-13.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-29 INSTRUCT ION CYCLE T IMES All instruc tions in this f orm at have an equivalent ARM instr uction as s hown in Table 4-13. T he ins truction cycle times for the THUMB inst ruction are identic al to that of the equivalent ARM instr uction.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-30 FORMA T 13: A DD OFFSE T TO S TACK POINTER [6:0] 7-bit Immediate Value [7] Sign Flag 0 = Offset is positive 1 = Offset is negative 15 0 1 14 10 01 13 12 11 SWord 7 1 0 0 7 8 9 6 00 S Figure 4-14.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-31 FORMA T 14: PUSH/POP REGISTERS [7:0] Register List [8] PC/LR Bit 0 = Do not store LR/Load PC 1 = Store LR/Load PC [11] Load/Store Bit 0 = Store to memory 1 = Load from memory 15 0 1 14 10 01 13 12 11 Rlist 1 L 0 7 8 9 1R Figure 4-15.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-32 INSTRUCT ION CYCLE T IMES All instruc tions in this f orm at have an equivalent ARM instr uction as s hown in Table 4-15. T he ins truction cycle times for the THUMB inst ruction are identic al to that of the equivalent ARM instr uction.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-33 FORMA T 15: MULTIPLE LOAD /STORE [7:0] Register List [10:8] Base Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory 15 0 1 14 10 10 13 12 11 Rlist 0 L 7 8 Rb Figure 4-16. Fo rmat 15 OPERA T ION Thes e instruct ions allow multiple loading and s toring of Lo r egisters .
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-34 FORMA T 16: CONDITIONA L BRANCH [7:0] 8-bit Signed Immediate [11:8] Condition 15 0 1 14 10 13 12 11 SOffset 8 1 7 8 Cond Figure 4-17. Fo rmat 16 OPERA T ION The instruc tions in this group all perf orm a conditional Branc h depending on the state of the CPSR c ondition codes.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-35 Table 4-17. The Conditional Branch Instructions (Continued) L THUM B assembler A RM equiv alent Description 1001 BLS label BLS label Branch if C.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-36 FORMA T 17 : SOFTWARE INTERRUPT [7:0] Comment Field 15 0 1 14 10 13 12 11 Value 8 1 7 8 10 9 1111 Figure 4-18. Fo rmat 17 OPERA T ION The SW I instr uction perfor ms a software interrupt. O n taking the SW I, the proces sor switches into ARM state and enters Supervis or (SVC) m ode.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-37 FORMA T 18 : UNCONDITIONA L BRANCH [10:0] Immediate Value 15 0 1 14 11 13 12 11 Offset11 0 10 0 Figure 4-19. Fo rmat 18 OPERA T ION This ins truction perform s a PC-relative Branch. The T HUMB assembler sy ntax is shown below.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-38 FORMA T 19: LONG BRA NCH W ITH LINK [10:0] Long Branch and Link Offset High/Low [11] Low/High Offset Bit 0 = Offset high 1 = Offset low 15 0 1 14 11 13 12 11 Offset 1 10 H Figure 4-20. Fo rmat 19 OPERA T ION This form at s pecifies a long branch with link.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-39 INSTRUCT ION CYCLE T IMES This instruct ion form at does not have an equivalent ARM ins truction.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-40 INSTRUCTION SET EXAMPLES The f ollowi ng ex amples s how ways in which the THUMB instr uctions ma y be used to generate s mall and ef ficient code. Each exam ple als o shows the ARM equivalent so these m ay be compar ed.
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-41 GENERA L PURPOSE SIGNED DIVIDE This exam ple shows a general purpos e signed divide and rem ainder routine in both T hum b and ARM code.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-42 Now fix up the signs of the quotient (R0) and r emainder (R1) POP { R2, R3} ; G et dividend/divisor signs back EOR R3, R2 ; Result sign EOR R0, .
S3C2440A RISC MICROPROCESSOR THUMB INSTRUCTION SET 4-43 DIVISION BY A CONST ANT Division by a constant can often be perf orm ed by a short fixed sequenc e of shif ts, adds and s ubtracts. Here is an exam ple of a divide by 10 routine based on the algorithm in the ARM Cook book in both Thum b and ARM code.
THUMB INSTRUCTION SET S3C2440A RISC MICROPROCESSOR 4-44 NOTES.
S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER 5-1 5 MEMORY CONTROLLER OVERVIEW The S3C2440A m em ory controller provides mem or y c ontrol signals that ar e required f or external m em ory access.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-2 0x0000 _000 0 0x0800 _000 0 0x1000 _000 0 0x1800 _000 0 0x2000 _000 0 0x2800 _000 0 0x3000 _000 0 0x3800 _000 0 0x4000 0_00 00 SROM / SDRA M (nGCS7) .
S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-3 FUNCTION DESCRIPTION BA NK0 BUS WIDT H The data bus of BANK0 (nGC S0) should be conf igured with a width as one of 16-bit and 32-bit ones .
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-4 SDRA M BANK A DDRESS PIN CO NNECTIO N EXA M PLE Table 5- 2. SDRA M Bank Address Configuration Example Bank Size Bus Width Base Component M emory Conf.
S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-5 nWAIT PIN OPERA T ION If the W AIT bit(W Sn bit in BW SCON) cor responding to each m em ory bank is enabled, the nO E duration should be prolonged by the external nW AIT pin while the m em ory bank is active.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-6 nXBREQ/nXBA CK Pin Operation If nXBREQ is asser ted, the S3C2440A will respond by low ering nXBACK. If nXBACK=L, the addres s/data bus and me mor y control signals are in Hi-Z state as shown in Table 1- 1.
S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-7 ROM M emory Interface Examples A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 nWE nOE nGCSn A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE Figure 5-4.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-8 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE.
S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-9 SRA M M emory Interface Examples A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-10 SDRA M M emory Interface Examples A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 .
S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-11 PROGRAMM A BL E A CCESS CY CLE Tcoh Tcos Tacs HCLK A[24:0] nGCS nOE nWE nWBE D[31:0](R) D[31:0] (W) Tacc Tacp Tcah Tacs = 1 cycle Tcos = 1 cycle Tacc = 3 cycles Tacp = 2 cycles Tcoh = 1 cycle Tcah = 2 cycles Figure 5-12.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-12 MCLK SCKE nSCS nSCAS ADDR A10/AP RA nSRAS BA DATA (CL2) DATA (CL3) nWE DQM Trp Trcd RA Ca Da Da BA BA Cb Cc Cd Ce Db Dc Dd De Db Dc Dd De BA BA BA BA BA Bank Precharge Row Active Write Read (CL = 2, CL = 3, BL = 1) Trp = 2 cycle Tcas = 2 cycle Trcd = 2 cycle Tcp = 2 cycle Figure 5-13.
S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-13 BUS WIDTH & W A IT CONTROL REGIST ER (BWSCON) Register Address R/W Description Reset Value BW SCON 0x48000000 R/W Bus width & wait status contr ol register 0x000000 BWSCON Bit Descrip tion Initial state ST7 [31] Determines SRAM f or using UB/LB f or bank 7.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-14 BUS WIDTH & W A IT CONTROL REGIST ER (BWSCON) (Continued) W S2 [10] Determ ines W AIT status f or bank 2.
S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-15 BA NK CONT ROL REGISTER (BANKCONn: nGCS0-nGCS5) Register Address R/W Description Reset Value BANKCON0 0x48000004 R/W Bank 0 contr ol r.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-16 BA NK CONT ROL REGISTER (BANKCONn: nGCS6-nGCS7) Register Address R/W Descrip tion Reset Value BANKCON6 0x4800001C R/W Bank 6 control regis ter 0x180.
S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-17 REFRESH CONTROL REGIST ER Register Address R/W Descript ion Reset Value REFRESH 0x48000024 R/W SDRAM refres h control regis ter 0xac00.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-18 BA NKSIZE REGIST ER Register Address R/W Descriptio n Reset Value BANKSIZE 0x 48000028 R/W Flexible bank size register 0x 0 BA NKSIZE Bit Descriptio n Initial State BURST_EN [7] ARM cor e burst operation enable.
S3C2440A RISC MICROPROCESSO R MEMORY CONTROLLER DEC.13, 2002 5-19 SDRA M M ODE REGIST ER SET REGIST ER (M RSR) Register Address R/W Descriptio n Reset Value MRSRB6 0x4800002C R/W Mode register set reg.
MEMORY CONTROLLER S3C2440A RISC MICROPROCESSOR 5-20 NOT ES.
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-1 6 NA ND FLA SH CONTORLLER OVERVIEW In recent tim es, NO R flash m em ory gets high in price while an SDRAM and a NAND flash m em ory is com paratively economical , m otivating s ome us ers to exec ute the boot code on a NAND f lash and execute the main c ode on an SDRAM.
NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-2 BLOCK DIA GRAM zmy ljjGn U z Gz O[riGzyhtP z Gz j .
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-3 PIN CONFIGURA T ION OM[1:0] = 00: Enable NAND f lash m em ory boot NCON : NAND f lash m em ory selection(Norm al / Advance) 0: Norm al NA.
NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-4 NA ND FLASH MEMORY TIM ING HCLK CLE / ALE nW E T AC LS T WR PH 0 TWR P H 1 DATA COMMAND / A DDRESS Figure 6-3.
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-5 SOFTWA RE MODE S3C2440A supports only sof tware mode acces s. Using this mode, you can com pletely access the NAND flas h mem ory. The NAND Flash Contr oller supports direct acc ess interf ace with the NAND flash m em ory.
NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-6 Data Register Configur ation 1) 16-b it NA ND F lash M emory Interface A . W ord A ccess Register Endian Bit [31:24] Bit [23: 16] Bit [15:8] Bit.
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-7 ECC(Error Correctio n Code) NAND Flash controller consis ts of f our ECC (Err or Correc tion Code) m odules.
NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-8 ECC MO DULE FEA T URES ECC generation is contr olled by the ECC Loc k ( MainECCLock , SpareECCLock ) bit of the Control register .
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-9 NA ND FLASH MEMORY M A PPING Not Used SFR Area Not Used BootSRAM (4KB) 0xFFFF_FFFF 0x6000_0000 0x4800_0000 0x4000_0000 SFR Area Not Used SDRAM (B.
NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-10 NA ND FLASH MEMORY CONFIGURA T ION I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 R/ B WE ALE CLE CE RE RnB nFW E ALE CLE nFCE nFRE DATA[ 7] DATA[ 6] .
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-11 Nand Flash configuration Register Register A ddress R/W Descriptio n Reset Value NFCONF 0x4E000000 R/W NAND Flash Configuration register 0x00001.
NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-12 AdvFlash (Read only) [3] Advance NAND f lash m em ory for auto-booting 0: Support 256 or 512 byte/page NAND flash mem ory 1: Support 1024 or 2048 byte/page NAND flash mem ory This bit is determ ined by NCON0 pin status during res et and wake-up f rom sleep m ode.
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-13 CONTROL REGIST ER Register A ddress R/W Descriptio n Reset Value NFCONT 0x4E000004 R/W NAND Flash control register 0x0384 NFCONT Bit Descript io.
NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-14 0: Unlock Spare ECC 1: Lock Spare ECC Spare area ECC status register is NFSECC(0x4E000034), MainECCLock [5] Lock Main data area ECC generation .
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-15 COMM AND REGISTER Register A ddress R/W Descriptio n Reset Value NFCMMD 0x4E000008 R/W NAND Flash com m and set r egister 0x00 NFCM MD Bit Descr.
NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-16 MAIN DA T A AREA REGIST ER Register A ddress R/W Descriptio n Reset Value NFMECCD0 0x4E000014 R/W NAND Flash ECC 1 st and 2 nd register f or m ain data read Note: Refer to ECC M ODULE FEA TURES in Page 6-8.
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-17 SPA RE AREA ECC REGIST ER Register A ddress R/W Descriptio n Reset Value NFSECCD 0x 4E00001C R/W NAND Flash ECC(Error Correction Code) regis ter.
NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-18 NFCON STATUS REGISTER Register A ddress R/W Descriptio n Reset Value NFSTAT 0x4E000020 R/W NAND Flash operation status regis ter 0xX X00 NFSTAT.
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-19 ECC0/1 STATUS REGISTER Register A ddress R/W Description Reset Value NFESTAT 0 0x 4E000024 R/W NAND F lash ECC Status regist er for I/O [7:0] 0x.
NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-20 MAIN DA T A AREA ECC0 STATUS REGISTER Register A ddress R/W Descriptio n Reset Value NFMECC0 0x4E00002C R NAND Flash ECC register for data[7:0].
S3C2440A RISC MICROPROCESSOR NAND FLASH CONTROLLER 6-21 BLOCK ADDRESS REGISTER Register A ddress R/W Descriptio n Reset Value NFSBLK 0x4E000038 R/W NAND Flash progr am mable s tart block address 0x000000 NFEBLK 0x 4E00003C R/W NAND F lash program m able end block address Nand Flash can be progr am med between star t and end address.
NAND FLA SH CONTROLLER S3C2440A RISC MICROPROCESSOR 6-22 The NFSLK and NF EBLK can be changed while Soft loc k bit( NFCONT [12]) is enabled. But cannot be c hanged when Lock-tight bit( NFCONT [13]) is set.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAGEMENT 7 - 1 7 CLOCK & POWER MA NA GEMENT OVERVIEW The Cloc k & Power m anagem ent block consis ts of thr ee parts: Cloc k c ontrol, USB control, and Power contr ol.
CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 2 FUNCTIONA L DESCRIP TION CLOCK A RCHIT ECTURE Figure 7-1 shows a bloc k diagr am of the clock arc hitecture. T he m ain cloc k source com es from an exter nal cr y stal (XT Ipll) or an external cloc k ( EXT CLK).
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 3 Nand Fl a sh Contro ller OSC MPLL UPLL CLKCNTL FCL K HDIVN PDIVN Mpll Contr ol Signal Upl l POWC NTL FH P USBCNTL Test mo de OM[1:0 ] .
CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 4 PHA SE LOCKED LOOP (P LL) The MPLL within the clock generator, as a circuit, s y nc hronizes an output signal with a referenc e input s ignal in frequenc y and phase.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 5 Divider P Loop Filter Fin M[7:0] S[1:0] PFD Divider M P[5:0] F vco PUMP VCO Divider S F ref MPLL,U PLL R C Internal C LF External MPLLCAP, UPLLCAP Figure 7-2.
CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 6 CLOCK CONTROL LOGIC The Clock Control Logic determ ines the clock sourc e to be used, i.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 7 Change PLL Se ttings In Normal Oper ation M ode During the operation of the S3C2440A in NO RMAL m ode, the user can change the fr equency by writing the PMS value and the PLL lock tim e will be automatically inserted.
CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 8 FCLK, HCLK, and PCLK FCLK is used by ARM920T. HCLK is used f or AHB bus, which is us ed by the ARM920T, the m em ory controller, the interr upt controller, the LCD controller, the DMA and USB hos t block .
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 9 NOTE 1. CLKDIVN s hould be set car efully not to exceed the limit of HCLK and PCLK. 2. If HDIVN is not 0, the CPU bus m ode has to be changed from the f ast bus m ode to the asynchronous bus mode us ing following instruc tions(S3C2440 does not s upport synchronous bus m ode).
CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 10 POWER MANA GEM ENT The Power Managem ent block contr ols the system c locks by software for the reduc tion of power cons umption in the S3C2440A. Thes e schem es are r elated to PLL, clock control logic s (FCLK, HCLK, and PCLK) and wakeup signals.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 11 IDLE SLEEP NORMAL (SLOW _BIT=0) SLOW (SLOW _BIT=1) IDLE_BIT=1 Interrupts, EINT[0:23], RTC alarm SLEEP BIT=1 EINT[15:0], RTC alarm RESET Figure 7-8. Po wer M anagemen t State Diag ram Tabl e 7-2.
CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 12 NORMAL Mode In Normal m ode, all peripherals and the basic blocks including power m anagement bloc k, the CPU core, the bus controller, the mem or y c ontroller, the interr upt controller, DMA, and the external m aster m ay operate com pletely.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 13 Users can change the frequency by enabling SLOW m ode bit in CLKSLOW register in PLL on state. T he SLOW clock is generated dur ing the SLOW m ode. Figure 7-11(Pleas e check the figure correc tly) s hows the timing diagram .
CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 14 If the user switches fr om SLOW m ode to Norm al m ode by disabling SLOW _BIT and MPLL_OF F bit sim ultaneously in the CLKSLO W register , the f requency is changed just af ter the PLL lock tim e.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 15 SLEEP M ode The bloc k dis connects the inter nal power. So, there occurs no power consum ption due to CPU and the internal logic exc ept the wake-up logic in this m ode. Activating the SLEEP m ode requires two independent power sourc es.
CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 16 Follow the Pro cedure to W ake-up f rom SLEEP mode 1. T he internal r eset signal will be asser ted if one of the wake-up sour ces is issued. It’s ex actly same with the case of the assert ion of the exter nal nRESET pin.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 17 Power Control of VDDi and VDDiar m In SLEEP mode, VDDi, VDDiar m , VDDMPLL and VDDUPLL will be turned off, which is controlled by PW REN pin. If PW REN signal is ac tivated(H), VDDi and VDDiarm are s upplied by an exter nal voltage r egulator.
CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 18 Signaling EINT[15:0] for Wakeup The S3C2440A c an be woken up fr om SLEEP mode only if the following conditions are m et. a) Level signals (H or L) or edge s ignals (rising, f alling or both) are as serted on EINT n input pin.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 19 Outp ut Po rt Stat e and SLEEP M od e The output port s hould have a proper logic level in power off m ode, which mak es the current consum ption minim ized. If there is no load on an output port pin, H level is pref erred.
CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 20 CLOCK GENER ATOR & POWER MA NAGEM ENT SPECIA L REGISTER LOCK TIM E COUNT REGIST ER (LOCKT IM E) Register Address R/W Descripti on.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 21 PLL CONTROL REGIST ER (M PLLCON & UPLLCON) Register Address R/W Descripti on Reset Value MPLLCON 0x4C000004 R/W MPLL conf igurati.
CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 22 CLOCK CONTROL REGIST ER (CLKCON) Register Address R/W Descripti on Reset Value CLKCON 0x4C00000C R/W Clock generator control register 0xFFFFF0 CLKCON Bit Descript ion In itial State AC97 [20] Control PCLK into AC97 bloc k.
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 23 CLOCK SLOW CONTROL (CLKSLOW ) REGISTER Register Address R/W Descripti on Reset Value CLKSLOW 0x 4C000010 R/W Slow clock control r egi.
CLOCK & POWER MANA GEM ENT S3C2440A RISC MICROPROCESSOR 7 - 24 CLOCK DIVIDER CONTROL (CLKDIVN) REGISTER Register Address R/W Descripti on Reset Value CLKDIVN 0x4C000014 R/W Cloc k divider control .
S3C2440A RISC MICROPROCESSOR CLOCK & POWER MANAG EM ENT 7 - 25 CA M ERA CLOCK DIVIDER ( CA M DIVN) REGIST ER Register Address R/W Descript ion Reset Value CAMDIVN 0x 4C000018 R/W Cam era c lock divider register 0x00000000 CA M DIVN Bit Descripti on Initial Stat e DVS_EN [12] 0:DVS OFF ARM core will run norm ally with FCLK(MPLLout).
S3C2440A RISC MICROPROC ESSOR DMA 8-1 8 DMA OVERVIEW The S3C2440A s upports f our-channel DMA c ontroller located between the system bus and the peripheral bus. Each channel of DMA controller c an perfor m data movem ents between devices in the sy s tem bus and/or peripheral bus with no restr ictions.
DMA S3C2440A RISC MICROPROCESSO R 8-2 DMA REQUEST SOURC ES Each channel of the DMA controller can select one of the DMA reques t source am ong four DMA sourc es, if H/W DMA request m ode is s elected by DCON register. (Note that if S/W request m ode is selected, this DMA request sources have no m eaning at all.
S3C2440A RISC MICROPROC ESSOR DMA 8-3 EXTERNAL DMA DREQ/DACK PROTOCOL There are thr ee ty pes of exter nal DMA request/ac knowledge protocols (Single servic e Demand, Single s ervice Handshak e and W hole service Handshak e m ode). Eac h ty pe def ines how the signals like DMA request and ack nowledge are related to these protoc ols.
DMA S3C2440A RISC MICROPROCESSO R 8-4 Demand/Handshake M ode Co mparison Demand and Hands hake m odes are related to the protocol between XnX DREQ and XnX DACK. Figure 8-2 s hows the diff erences between the two modes . At the end of one trans fer (Single/Bur st transf er), DMA c heck s the state of double-synched XnXDREQ.
S3C2440A RISC MICROPROC ESSOR DMA 8-5 Transfer Size - There ar e two different tr ansfer sizes; unit and Burst 4. - DMA holds the bus f irm ly dur ing the transf er of the c hunk of data.
DMA S3C2440A RISC MICROPROCESSO R 8-6 EXA MPLES Single service in Demand M ode w ith Unit Transfer Siz e The as sertion of XnXDREQ will be a need for every unit transfer (Single service m ode). T he operation c ontinues while the XnXDREQ is asserted ( Dem and m ode), and one pair of Read and W r ite (Single transf er size) is perform ed.
S3C2440A RISC MICROPROC ESSOR DMA 8-7 DMA SPECIA L REGISTERS Each DMA channel has nine control regis ters (36 in total since ther e are four channels for DMA controller) . Six of the control regis ters contr ol the DMA transf er, and other three ones m onitor the s tatus of DMA controller.
DMA S3C2440A RISC MICROPROCESSO R 8-8 DMA INITIA L DEST INA TION (DIDST) REGIST ER Register Address R/W Description Reset Value DIDST0 0x4B000008 R/W DMA 0 initial destination register 0x 00000000 DID.
S3C2440A RISC MICROPROC ESSOR DMA 8-9 DMA CONTROL (DCON) REGISTER Register Address R/W Description Reset Value DCON0 0x4B000010 R/W DMA 0 control register 0x00000000 DCON1 0x4B000050 R/W DMA 1 control.
DMA S3C2440A RISC MICROPROCESSO R 8-10 DCONn Bit Descriptio n Initial State SERVMODE [27] Select the service m ode between Single ser vice m ode and W hole service m ode. 0: Single service m ode is selected in which af ter each atom ic tr ansfer (single or bur st of length f our) DMA s tops and waits for another DMA request.
S3C2440A RISC MICROPROC ESSOR DMA 8-11 DMA STATUS (DSTAT) REGIST ER Register Address R/W Description Reset Value DSTAT 0 0x4B000014 R DMA 0 count r egister 000000h DSTAT 1 0x4B000054 R DMA 1 count r e.
DMA S3C2440A RISC MICROPROCESSO R 8-12 DMA CURRENT SOURCE (DCSRC) REGISTER Register Address R/W Description Reset Value DCSRC0 0x 4B000018 R DMA 0 c urrent Sourc e Register 0x00000000 DCSRC1 0x 4B0000.
S3C2440A RISC MICROPROC ESSOR DMA 8-13 DMA MASK TRIGGER (DM ASKTRIG) REGIST ER Register Address R/W Description Reset Value DMASKTRIG0 0x4B000020 R/W DMA 0 m as k trigger register 000 DMASKTRIG1 0x4B0.
DMA S3C2440A RISC MICROPROCESSO R 8-14 NOT ES.
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-1 9 I/O PORTS OVERVIEW S3C2440A has 130 m ulti-func tional input/output port pins and there ar e eight ports as s hown below: - Port A(G PA): 25-output port - .
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-2 Table 9- 1. S3C2440A Po rt Config uration( Sheet 1 of 5) Port A Selectable P in Functions GPA22 Output only nFCE – – GPA21 Output only nRST OUT – – G.
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-3 Table 9- 1. S3C2440A Po rt Config uration( Sheet 2 of 5) Port B Selectable P in Functions GPB10 Input/output nX DREQ0 – – GPB9 Input/output nXDACK0 – .
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-4 Table 9- 1. S3C2440A Po rt Config uration( Sheet 3 of 5) Port D Selectable P in Functions GPD15 Input/output VD23 nSS0 – GPD14 Input/output VD22 nSS1 – G.
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-5 Table 9- 1. S3C2440A Po rt Config uration( Sheet 4 of 5) Port F Selectable Pin Func tions GPF7 Input/output EINT7 – – GPF6 Input/output EINT6 – – GPF.
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-6 Table 9- 1. S3C2440A Po rt Config uration( Sheet 5 of 5) Port H Selectable P in Functions GPH10 Input/output CLKO UT1 – – GPH9 Input/output CLKOUT0 – .
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-7 PORT CONTROL DESCRIPTIONS PORT CONFIGURATION REGISTER (GPA CON-GPJCON) In S3C2440A, mos t of the pins are m ultiplexed pins. So, It is determ ined which function is selected f or each pins . The PnCO N(port control r egister) deter m ines which function is used f or each pin.
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-8 I/O PORT CONTROL REGISTER PORT A CONTROL REGISTERS(GPA CON, GPADA T) Register Address R/W Description Reset Value GPACON 0x56000000 R/W Conf igures the pins of port A 0x ffffff GPADAT 0x 56000004 R/W The data regis ter for port A Undef.
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-9 GPA DAT Bit Description GPA[24:0] [24:0] W hen the port is configur ed as output port, the pin st ate is the sam e as the corres ponding bit. W hen the port is conf igured as f unctional pin, the undef ined value will be read.
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-10 PORT B CONT ROL REGISTERS(GPBCON, GPBDAT, GPBUP) Register Address R/W Descript ion Reset Value GPBCON 0x56000010 R/W Configur es the pins of port B 0x0 GPBDAT 0x56000014 R/W T he data regist er for por t B Undef.
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-11 PORT C CONT ROL REGISTERS(GPCCON, GPCDAT, GPCUP) Register Address R/W Descript ion Reset Value GPCCON 0x56000020 R/W Conf igures the pins of port C 0x0 GPCDAT 0x56000024 R/W The data regis ter for por t C Undef.
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-12 GPCDA T Bit Description GPC[15:0] [15:0] W hen the port is configur ed as input port, the cor responding bit is the pin state. W hen the port is c onfigured as output port, the pin state is the s ame as the corres ponding bit.
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-13 PORT D CONT ROL REGISTERS(GPDCON, GPDDAT, GPDUP) Register Address R/W Descript ion Reset Value GPDCON 0x56000030 R/W Conf igures the pins of port D 0x0 GPDDAT 0x56000034 R/W The data regis ter for por t D Undef.
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-14 GPDDA T Bit Description GPD[15:0] [15:0] W hen the port is configur ed as input port, the cor responding bit is the pin state. W hen the port is c onfigured as output port, the pin state is the s ame as the corres ponding bit.
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-15 PORT E CO NTRO L REGIST ERS(GPECON , GPEDA T, GPEUP) Register Address R/W Descript ion Reset Value GPECON 0x56000040 R/W Configur es the pins of port E 0x0 GPEDAT 0x56000044 R/W T he data regist er for por t E Undef.
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-16 . GPEDA T Bit Description GPE[15:0] [15:0] W hen the port is conf igured as an input por t, the corres ponding bit is the pin state. W hen the port is conf igured as an output port, the pin s tate is the sam e as the corres ponding bit.
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-17 PORT F CONT ROL REGISTERS(GPFCON, GPFDAT) If GPF0 - GPF7 will be used for wake-up s ignals at power down mode, the ports will be set in interrupt m ode.
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-18 PORT G CONTROL REGISTERS(GPGCON, GPGDA T ) If GPG 0 - GPG7 will be used f or wake- up signals at Sleep m ode, the ports will be set in inter rupt m ode.
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-19 GPGDAT Bit Description GPG[15:0] [15:0] W hen the port is configur ed as an input port, the cor responding bit is the pin s tate. W hen the port is conf igured as an output port, the pin s tate is the sam e as the corres ponding bit.
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-20 PORT H CONT ROL REGISTERS(GPHCON, GPHDAT) Register Address R/W Descript ion Reset Value GPHCON 0x56000070 R/W Conf igures the pins of port H 0x0 GPHDAT 0x56000074 R/W The data regis ter for por t H Undef.
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-21 GPHDA T Bit Descrip tion GPH[10:0] [10:0] W hen the port is c onfigured as an input port, the corr esponding bit is the pin st ate. W hen the port is conf igured as an output port, the pin s tate is the sam e as the corres ponding bit.
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-22 PORT J CONT ROL REGISTERS(GPJCON, GPJDAT) Register Address R/W Descript ion Reset Value GPJCON 0x 560000d0 R/W Configures the pins of por t J 0x0 GPJDAT 0x560000d4 R/W T he data register for por t J Undef .
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-23 GPJDA T Bit Description GPJ15:0] [12:0] W hen the port is configured as an input port, the corr esponding bit is the pin s tate. W hen the port is conf igured as an output port, the pin s tate is the sam e as the corres ponding bit.
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-24 MISCELLANEOUS control register(MISCCR) In Sleep mode, the data bus (D[31:0] or D[15:0] c an be set as Hi-Z and O utput ‘0’ state. But, becaus e of the character istics of IO pad, the data bus pull- up resisters have to be turned on or of f to reduc e the power consum ption.
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-25 CLKSEL1 (1) [10:8] Select source c lock with CLKOUT1 pad 000 = MPLL output 001 = UPLL output 010 = RTC cloc k output 011 = HCLK 100 = PCLK 101 = DCLK1 11x =.
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-26 DCLK CONTROL REGIST ERS(DCLKCON) Register Address R/W Descript ion Reset Value DCLKCON 0x56000084 R/W DCLK0/1 Control Regis ter 0x0 DCLKCON Bit Descript ion DCLK1CMP [27:24] DCLK1 Com pare value clock toggle value.
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-27 EXTINTn(External Interrupt Control Re gister n) The 8 ex ternal interrupts c an be requested by various signaling m ethods. T he EXT INT regis ter conf igures the signaling m ethod between the level trigger and edge trigger f or the external inter rupt request, and als o configur es the signal polarity.
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-28 EXTINT 1 Bit Description FLTEN15 [31] F ilter Enable for EINT15 0 = Filter Disable 1= Filter Enable EINT15 [30:28] Setting the signaling m ethod of the EINT 15.
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-29 EXTINT 2 Bit Descriptio n Reset Value FLTEN23 [31] Filter Enable for EINT 23 0 = Filter Disable 1= Filter Enable 0 EINT23 [30:28] Setting the signaling m ethod of the EINT 23.
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-30 EINT17 [6:4] Setting the signaling m ethod of the EINT 17. 000 = Low level 001 = High level 01x = Falling edge trigger ed 10x = Ris ing edge triggered 11x =.
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-31 EINTFLTn(External Interrupt Filte r Register n) To r ecognize the level interrupt, the valid logic level on EXT INT n pin m ust be retained f or 40ns at leas t because of the noise filter .
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-32 EINTM ASK(External Interrupt M ask Regist er) Register Address R/W Descriptio n Reset Value EINTMASK 0x560000a4 R/W External interupt m ask Register 0x 000 .
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-33 EINTPEND(Exte rnal Interr upt Pending Register ) Register Address R/W Descriptio n Reset Value EINTPEND 0x560000a8 R/W External interupt pending Regis ter 0.
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-34 EINT5 [5] It is clear d by writing “ 1” 0 = not occur 1= oc cur interr upt 0 EINT4 [4] It is clear d by writing “ 1” 0 = not occur 1= oc cur interr .
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-35 GSTATUSn (G eneral Statu s Registers) Register Address R/W Descriptio n Reset Value GSTAT US0 0x560000ac R External pin status Not define GSTAT US1 0x560000.
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-36 DSCn (Drive Stre ngth Control) Control the Mem ory I/O drive strength Register Address R/W Descriptio n Reset Value DSC0 0x560000c4 R/W strength control r e.
S3C2440A RISC MICROPROCESSOR I/O PORTS 9-37 DSC1 Bit Description Reset Value DSC_SCK1 [29:28] SCLK1 Drive str ength. 00: 12mA 10: 10m A 01: 8mA 11: 6m A 00 DSC_SCK0 [27:26] SCLK0 Drive str ength. 00: 12mA 10: 10m A 01: 8mA 11: 6m A 00 DSC_SCKE [25:24] SCKE Drive strength.
I/O PORTS S3C2440A RISC MICROPROCESSOR 9-38 MSLCON (M emory S leep Control Register ) Select m em ory interface status when in SLEEP mode. Register Address R/W Descriptio n Reset Value MSLCON 0x560000cc R/W Mem ory Sleep Control Register 0x0 MSL CON Bit Descriptio n Reset Value PSC_DATA [11] DATA[31:0] pin st atus in Sleep m ode.
S3C2440A RISC MICROPROCESSOR PWM TIMER 10-1 10 PWM TIMER OVERVIEW The S3C2440A has five 16-bit tim ers . Tim er 0, 1, 2, and 3 have Pulse W idth Modulation (PW M) f unction. Tim er 4 has an internal timer only w ith no output pins. The tim er 0 has a dead-zone generator, which is us ed with a large current devic e.
PWM TIMER S3C2440A RISC MICROPROCESSO R 10-2 Clock Divider 5:1 MUX Dead Zone Generator TOUT0 TOUT1 TOUT2 Control Logic0 TCMPB0 TCNTB0 Control Logic1 TCMPB1 TCNTB1 5:1 MUX Clock Divider 5:1 MUX 5:1 MUX.
S3C2440A RISC MICROPROCESSOR PWM TIMER 10-3 PWM TIMER OPERA TION PRESCA LER & DIVIDER An 8-bit presc aler and a 4-bit divider m ak e the following output fr equencies: 4-bit divider settings Minimum resolution (prescaler = 0) M aximum resolutio n (prescaler = 255) Maximum in terval (TCNT Bn = 65535) 1/2 (PCLK = 50 MHz) 0.
PWM TIMER S3C2440A RISC MICROPROCESSO R 10-4 A UT O RELOA D & DOUBLE BUFFERING S3C2440A PW M Tim ers have a double buffering f unction, enabling the reload value changed f or the next tim er operation without s topping the current timer operation.
S3C2440A RISC MICROPROCESSOR PWM TIMER 10-5 TIM ER INITIALIZA TION USING M A NUAL UPDA TE BIT A ND INVERT ER BIT An auto reload oper ation of the timer occurs when the dow n c ounter reaches 0. So, a starting value of the TCNT n has to be def ined by the user in advance.
PWM TIMER S3C2440A RISC MICROPROCESSO R 10-6 TIM ER OPERA T ION TOUTn 12 4 6 50 110 40 40 60 20 3 79 1 0 5 8 11 Figure 10-4. Examp le of a T imer Operation The above Figur e 10-4 shows the res ult of the following proc edure: 1. Enable the auto re- load function.
S3C2440A RISC MICROPROCESSOR PWM TIMER 10-7 PULSE WIDTH M ODULATION (PWM ) Write TCMPBn = 60 Write TCMPBn = 50 Write TCMPBn = 40 Write TCMPBn = 30 Write TCMPBn = 30 Write TCMPBn = Next PWM Value 60 50 40 30 30 Figure 10-5. Examp le of PWM PW M function c an be implem ented by using the TCMPBn.
PWM TIMER S3C2440A RISC MICROPROCESSO R 10-8 OUTPUT LEVEL CONT ROL Inverter off Initial State Period 1 Period 2 Timer Stop Inverter on Figure 10-6. In verter On /Off The f ollowing procedure desc ribes how to m aintain TO UT as high or low (assum e the inverter is off ): 1.
S3C2440A RISC MICROPROCESSOR PWM TIMER 10-9 DEA D ZONE GENERATOR The Dead Zone is for the PW M control in a power device. T his f unction enables the inser tion of the tim e gap between a tur n-off of a switching device and a turn on of another switching device.
PWM TIMER S3C2440A RISC MICROPROCESSO R 10-10 DMA REQUEST M ODE The PW M tim er c an generate a DMA request at ever y spec ific tim e. The timer keeps DMA request signals (nDMA_REQ) low until the timer rece ives an ACK signal. W hen the tim er rec eives the ACK signal, it m ak es the request signal inac tive.
S3C2440A RISC MICROPROCESSOR PWM TIMER 10-11 PWM TIMER CONTROL REGIS TE RS TIM ER CONFIGURA T ION REGISTER0 (T CFG0) Tim er input c lock Frequency = PCLK / {prescaler value+1} / {divider value} {pres .
PWM TIMER S3C2440A RISC MICROPROCESSO R 10-12 TIM ER CONFIGURA T ION REGISTER1 (T CFG1) Register Address R/W Descrip tion Reset Valu e TCF G1 0x51000004 R/W 5-MUX & DMA m ode selecton r egister 0x.
S3C2440A RISC MICROPROCESSOR PWM TIMER 10-13 TIM ER CONTROL (T CON) REGISTER Register Address R/W Descriptio n Reset Value TCO N 0x51000008 R/W T imer c ontrol regis ter 0x00000000 TCO N Bit Description In itial state Tim er 4 auto reload on/of f [22] Determ ine auto reload on/off for Tim er 4.
PWM TIMER S3C2440A RISC MICROPROCESSO R 10-14 TCON (Continued) TCO N Bit Description In itial state Reserved [7:5] Reserved Dead zone enable [4] Determine the dead zone operation. 0 = Disable 1 = Enable 0 Tim er 0 auto reload on/of f [3] Deter m ine auto reload on/off for T im er 0.
S3C2440A RISC MICROPROCESSOR PWM TIMER 10-15 TIM ER 0 COUNT BUFFER REGIST ER & COM PA RE BUFFER REGIST ER (TCNT B0/TCM PB0) Register Address R/W Descriptio n Reset Value TCNT B0 0x5100000C R/W T i.
PWM TIMER S3C2440A RISC MICROPROCESSO R 10-16 TIM ER 1 COUNT BUFFER REGIST ER & COM PA RE BUFFER REGIST ER (TCNT B1/TCM PB1) Register Address R/W Descriptio n Reset Value TCNT B1 0x51000018 R/W T .
S3C2440A RISC MICROPROCESSOR PWM TIMER 10-17 TIM ER 2 COUNT BUFFER REGIST ER & COM PA RE BUFFER REGIST ER (TCNT B2/TCM PB2) Register Address R/W Descriptio n Reset Value TCNT B2 0x51000024 R/W T i.
PWM TIMER S3C2440A RISC MICROPROCESSO R 10-18 TIM ER 3 COUNT BUFFER REGIST ER & COM PA RE BUFFER REGIST ER (TCNT B3/TCM PB3) Register Address R/W Descriptio n Reset Value TCNT B3 0x51000030 R/W T .
S3C2440A RISC MICROPROCESSOR PWM TIMER 10-19 TIM ER 4 COUNT BUFFER REGIST ER (TCNT B4) Register Address R/W Descriptio n Reset Value TCNT B4 0x5100003C R/W T imer 4 count buff er register 0x00000000 T.
PWM TIMER S3C2440A RISC MICROPROCESSO R 10-20 NOTES.
S3C2440A RISC MICROPROCESSOR UART 11-1 11 UA RT OVERVIEW The S3C2440A Univers al Asynchronous Receiver and T ransm itter ( UART) provide three independent asynchronous serial I/O (SIO) ports, each of which can operate in Inter rupt-based or DMA-based m ode.
UART S3C2440A RISC MICROPROCESSO R 11-2 BLOCK DIA GRAM B uad- r at e G ener at or Con t r ol Uni t Transm i t ter R ecei ver P er i pher al B US TXD n C l o ck S our ce ( PC LK, FCLK/ n, U EXTCLK) RXD.
S3C2440A RISC MICROPROCESSOR UART 11-3 UA RT OPERA T ION The f ollowing sections desc ribe the UART operations that include data trans m ission, data reception, interrupt generation, baud-rate generation, Loopbac k m ode, Inf rared m ode, and auto f low control.
UART S3C2440A RISC MICROPROCESSO R 11-4 A uto Flow Control (A FC) The S3C2440A's UART 0 and UART 1 support auto f low control with nRTS and nCTS signals .
S3C2440A RISC MICROPROCESSOR UART 11-5 RS-232C interface If the user wants to connect the UART to m odem inter face ( instead of null m odem ), nRT S, nCTS, nDSR, nDT R, DCD and nRI s ignals are needed. In this cas e, the users can c ontrol these signals with general I/O ports by software becaus e the AFC does not suppor t the RS-232C interf ace.
UART S3C2440A RISC MICROPROCESSO R 11-6 UA RT Error Sta tus FIFO UART has the error status FIFO bes ides the Rx F IFO regis ter. T he error status F IFO indicates which data, am ong FIFO regist ers, is rec eived with an error. T he error interr upt will be issued only when the data, which has an er ror, is ready to read out.
S3C2440A RISC MICROPROCESSOR UART 11-7 Baud-rate Ge neration Each UART's baud- rate generator provides the serial clock for the transm itter and the receiver. The s ource cloc k for the baud-rate generator can be selected with the S3C2440A's internal system clock or UEX TCLK.
UART S3C2440A RISC MICROPROCESSO R 11-8 Infrared (IR) M od e The S3C2440A UART block supports infrar ed (IR) transm is sion and reception, which can be s elected by setting the Infrar ed-m ode bit in the UART line c ontrol register (ULCONn). F igure 11-4 illustrates how to implem ent the IR mode.
S3C2440A RISC MICROPROCESSOR UART 11-9 Start Bit Stop Bit Data Bits SIO Frame 0101001101 Figure 11-4. Serial I/O F rame Timing Diagram ( Normal UA RT ) 0 Start Bit Stop Bit Data Bits IR Transmit Frame Bit Time Pulse Width = 3/16 Bit Frame 00 0 01 1 1 1 1 Figure 11-5.
UART S3C2440A RISC MICROPROCESSO R 11-10 UA RT SPECIA L REGISTERS UA RT LINE CONTROL REGIST ER There ar e three UART line c ontrol register s including ULCON0, ULCO N1, and ULCON2 in the UART bloc k.
S3C2440A RISC MICROPROCESSOR UART 11-11 UA RT CONTROL REGIST ER There ar e three UART c ontrol register s including UCON0, UCON1 and UCO N2 in the UART bloc k.
UART S3C2440A RISC MICROPROCESSO R 11-12 Tx Inter rupt Type [9] Interrupt reques t ty pe. 0 = P uls e ( Interrupt is r equested as soon as the Tx buffer becom es empty in Non-FIFO m ode or reaches T x FIF O T rigger Level in FIFO mode.
S3C2440A RISC MICROPROCESSOR UART 11-13 UART CONTROL REGISTER (Continued) Trans m it Mode [3:2] Determ ine which function is currently able to write Tx data to the UART transm it buff er regis ter.
UART S3C2440A RISC MICROPROCESSO R 11-14 UA RT FIFO CONTROL REGIST ER There ar e three UART F IFO control r egisters inc luding UFCON0, UFCON1 and UF CON2 in the UART bloc k.
S3C2440A RISC MICROPROCESSOR UART 11-15 UA RT M ODEM CONT ROL REGIST ER There ar e two UART MODEM contr ol registers including UMCON0 and UMCON1 in the UART block .
UART S3C2440A RISC MICROPROCESSO R 11-16 UA RT TX/RX ST ATUS REGISTER There ar e three UART T x/Rx status regis ters including UT RSTAT 0, UT RSTAT 1 and UTRST AT2 in the UART block .
S3C2440A RISC MICROPROCESSOR UART 11-17 UA RT ERROR STATUS REGISTER There ar e three UART Rx error s tatus register s including UERST AT0, UERST AT1 and UERST AT2 in the UART block .
UART S3C2440A RISC MICROPROCESSO R 11-18 UA RT FIFO STATUS REGISTER There ar e three UART FIFO s tatus register s including UFST AT 0, UFSTAT 1 and UFST AT2 in the UART block .
S3C2440A RISC MICROPROCESSOR UART 11-19 UA RT M ODEM STATUS REGISTER There ar e two UART m odem status r egisters inc luding UMSTAT 0, UMSTAT 1 in the UART block .
UART S3C2440A RISC MICROPROCESSO R 11-20 UA RT TRANSMIT BUFFER REGIST ER (HOLDING REGIST ER & FIFO REGISTER) There ar e three UART tr ansm it buff er registers including UTX H0, UT XH1 and UT XH2 in the UART block . UTX Hn has an 8-bit data f or transm ission data.
S3C2440A RISC MICROPROCESSOR UART 11-21 UA RT BA UD RATE DIVISOR REGISTER There ar e three UART baud r ate divisor regis ters including UBRDIV0, UBRDIV1 and UBRDIV2 in the UART block .
UART S3C2440A RISC MICROPROCESSO R 11-22 NOT ES.
S3C2440A RISC MICROPROCESSO R USB HOST 12-1 12 USB HOST CONTROLLER OVERVIEW S3C2440A supports 2- port USB host interf ace as f ollows: • OHCI Rev 1.0 com patible • USB Rev1.
USB HOST S3C2440A RISC MICROPROCESSOR 12-2 USB HOST CONTR OLLER SPECIA L REGISTERS The S3C2440A USB hos t controller c omplies with OHCI Rev 1.0. Refer to Open Hos t Controller Interf ace Rev 1.
S3C2440A RISC MICROPROCESSOR USB DEVICE 13-1 13 USB DEVICE CONTROLLER OVERVIEW Universal Serial Bus (USB) device contr oller is des igned to provide a high perf orm ance fu ll speed func tion controller s olution with DMA interface. USB devic e controller allows bulk transfer with DMA, interrupt tr ansfer and control trans fer.
USB DEVICE S3C2440A RISC MICROPROCESSOR 13-2 SIE RT_VP_OUT RT_VM_IN RT_VP_IN RXD RT_UXSUSPEND RT_UX_OEN RT_VM_OUT MC_ADDR[13:0] SIU GFI FIFOs MCU & DMA I/F MC_DATA_IN[31:0] MC_DATA_OUT[31:0] USB_CLK SYS_CLK SYS_RESETN MC_WR WR_RDN MC_CSN MC_INTR DREQN[3:0] DACKN[3:0] Figure 13-1.
S3C2440A RISC MICROPROCESSOR USB DEVICE 13-3 USB DEVICE CON TROLLER SPECIA L REGISTERS This section des cribes detailed f unctionalities about register s ets of USB device c ontroller. All special f unction regis ter is byte-access ible or word-acc essible.
USB DEVICE S3C2440A RISC MICROPROCESSOR 13-4 EP2_DMA_CON Endpoint2 DMA c ontrol register 0x218( L) / 0x21B(B) EP2_DMA_UNIT Endpoint2 DMA unit counter regis ter 0x 21C(L) / 0x21F (B) EP2_DMA_FIFO Endpo.
S3C2440A RISC MICROPROCESSOR USB DEVICE 13-5 FUNCTIO N A DDRESS REGIST ER (FUNC_ADDR_REG) This register m aintains the USB device controller address as signed by the host. The Micro Contr oller Unit (MCU) writes the value received through a SET_ADDRESS des criptor to this register .
USB DEVICE S3C2440A RISC MICROPROCESSOR 13-6 POWER M A NAGEMENT REGIST ER (PWR_REG) This register ac ts as a power contr ol register in the USB block .
S3C2440A RISC MICROPROCESSOR USB DEVICE 13-7 INTERRUPT REGISTER (EP_INT _REG/USB_INT_REG) The USB cor e has two interrupt registers . T hese registers act as status register s for the MCU when it is interrupted. T he bits are clear ed by writing a ‘1’ ( not ‘0’) to each bit that was set.
USB DEVICE S3C2440A RISC MICROPROCESSOR 13-8 Register Address R/W Description Reset Valu e USB_INT_REG 0x 52000158(L) 0x5200015B(B) R/W (by te) USB interrupt pending/c lear register 0x 00 USB_INT_REG Bit M CU USB Description Initial State RESET Interrupt [2] R /CLEAR SET Set by the USB when it receives reset s ignaling.
S3C2440A RISC MICROPROCESSOR USB DEVICE 13-9 INTERRUPT ENA BLE REGIST ER (EP_INT_EN_REG/USB_INT _EN_REG) Corresponding to eac h interrupt regis ter, T he USB device controller also has two interrupt enable r egisters ( except resum e interrupt enable) .
USB DEVICE S3C2440A RISC MICROPROCESSOR 13-10 Register Address R/W Description Reset Value USB_INT_EN_REG 0x 520016C(L) 0x5200016F(B) R/W (by te) Determ ine which interrupt is enabled 0x04 INT_M ASK_R.
S3C2440A RISC MICROPROCESSOR USB DEVICE 13-11 FRA M E NUM BER REGISTER (FPAME_NUM 1_REG/FRA M E_NUM 2_REG) W hen the host transf ers USB pack ets, eac h Start Of Frame (SOF) pack et includes a fr am e number . The USB device controller catches this fr ame num ber and loads it into this regis ter autom atically.
USB DEVICE S3C2440A RISC MICROPROCESSOR 13-12 INDEX REGIST ER (INDEX_REG) The INDEX register is used to indicate c ertain endpoint register s eff ectively.
S3C2440A RISC MICROPROCESSOR USB DEVICE 13-13 END POINT0 CONT ROL STATUS REGISTER (EP0_CSR) This register has the control and st atus bits f or Endpoint 0. Since a contr ol transaction is involved with both IN and OUT tokens , there is only one CSR register, m apped to the IN CSR1 register.
USB DEVICE S3C2440A RISC MICROPROCESSOR 13-14 END POINT IN CONT ROL STATUS REGISTER (IN_CSR1_REG/IN_CSR2_REG) Register Address R/W Descript ion Reset Value IN_CSR1_REG 0x52000184(L) 0x52000187(B) R/W .
S3C2440A RISC MICROPROCESSOR USB DEVICE 13-15 Register Address R/W Descript ion Reset Value IN_CSR2_REG 0x52000188(L) 0x5200018B(B) R/W (by te) IN END POINT contr ol status regis ter2 0x20 IN_CSR2_REG.
USB DEVICE S3C2440A RISC MICROPROCESSOR 13-16 END POINT OUT CONTROL ST A T US REGISTER (OUT _CSR1_REG/OUT _CSR2_REG) Register Address R/W Descript ion Reset Value OUT _CSR1_REG 0x52000190(L) 0x5200019.
S3C2440A RISC MICROPROCESSOR USB DEVICE 13-17 Register Address R/W Descript ion Reset Value OUT _CSR2_REG 0x52000194(L) 0x52000197(B) R/W (by te) End Point out control status register 2 0x00 OUT_CSR2_.
USB DEVICE S3C2440A RISC MICROPROCESSOR 13-18 END POINT OUT WRITE COUNT REGIST ER (OUT_FIFO_CNT 1_REG/OUT_FIFO_CNT 2_REG) Thes e registers maintain the num ber of bytes in the packet as the num ber is unloaded by the MCU.
S3C2440A RISC MICROPROCESSOR USB DEVICE 13-19 DMA INTERFA CE CONT ROL REGISTER (EPN_DM A _CON) Register Address R/W Description Reset Valu e EP1_DMA_CON 0x52000200(L) 0x52000203(B) R/W (by te) EP1 DMA.
USB DEVICE S3C2440A RISC MICROPROCESSOR 13-20 DMA UNIT COUNTER REGIST ER (EPN_DM A _UNIT ) This register is valid in Dem and mode. In other m odes, this regis ter value m ust be set to ‘0x 01’ Reg.
S3C2440A RISC MICROPROCESSOR USB DEVICE 13-21 DMA FIFO COUNTER REGISTER (EPN_DM A _FIFO) This regis ter has values in byte siz e in FIFO to be transferred by DMA. In case of OUT _DMA_RUN enabled, the value in OUT FIFO W rite Count Regis ter1 will be loaded in this regis ter autom atically.
USB DEVICE S3C2440A RISC MICROPROCESSOR 13-22 DMA TOT A L TRANSFER COUNTER REGIST ER (EPn_DM A_TTC_L ,M,H) This register s hould have total number of bytes to be transfer red using DMA (total 20- bit counter).
S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-1 14 INTERRUPT CONTROLLER OVERVIEW The interrupt c ontroller in the S3C2440A rec eives the request f rom 60 interrupt s ources. T hese inter rupt sourc es are provided by internal peripherals such as DMA contr oller, UART , IIC, and others.
INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-2 INTERRUPT CONT ROLLER OPERATION F-bit and I-bit of Progra m Status Register (PSR) If the F-bit of PSR in ARM920T CPU is set to 1, the CPU does not accept the Fas t Interrupt Request ( FIQ) f rom the interrupt controller.
S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-3 INTERRUPT SOURCES The interr upt controller s upports 60 interr upt sources as shown in the table below.
INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-4 INTERRUPT SUB SOURCES Sub Sources Descriptio ns Source INT_AC97 AC97 interr upt INT_W DT _AC97 INT_W DT W atchdoc interrupt INT_W DT _AC97 INT_CA.
S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-5 INTERRUPT PRIORITY GENERATING BLOCK The priority logic f or 32 interrupt requests is com posed of se ven rotation based arbiters: six first-level arbiter s and one second-level ar biter as shown in Figur e 14-1 below.
INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-6 INTERRUPT PRIORITY Each arbiter can handle six interr upt requests based on the one bit arbiter m ode contr ol (ARB_MODE) and two bits of s election contr ol signals (ARB_SEL) as follows: If ARB_SEL bits ar e 00b, the priority order is REQ0, REQ1, REQ2, REQ 3, REQ4, and REQ5.
S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-7 INTERRUPT CONTROLLER SPECIA L REGISTERS There ar e five contr ol registers in the interrupt contr oller: sour ce pending r egister, interrupt m ode register , m ask register, pr iority register, and interrupt pending regist er.
INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-8 SRCPND Bit Description Initial State INT_ADC [31] 0 = Not requested, 1 = Reques ted 0 INT_RT C [30] 0 = Not reques ted, 1 = Requested 0 INT_SPI1 .
S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-9 . INTERRUPT MO DE (INTM OD) REGIST ER This r egister is com posed of 32 bits each of w hich is r elated to an interrupt source. If a specific bit is set to 1, the corres ponding interrupt is proces sed in the FIQ (fas t interrupt) m ode.
INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-10 INTM OD Bit Description Initial State INT_ADC [31] 0 = IRQ, 1 = FIQ 0 INT_RT C [30] 0 = IRQ, 1 = FIQ 0 INT_SPI1 [29] 0 = IRQ, 1 = F IQ 0 INT_UAR.
S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-11 INTERRUPT MASK (INTM SK) REGISTER This register als o has 32 bits eac h of which is r elated to an interrupt sour ce.
INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-12 INTM SK Bit Description Initial State INT_ADC [31] 0 = Service available, 1 = Mas ked 1 INT_RT C [30] 0 = Ser vice available, 1 = Mask ed 1 INT_.
S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-13 PRIORITY REGIST ER (PRIORIT Y) Register Address R/W Description Reset Value PRIORITY 0x4A00000C R/W IRQ priority control register 0x7F PRIORITY.
INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-14 INTERRUPT PENDING (INTPND) REGIST ER Each of the 32 bits in the interrupt pending regis ter shows whether the c orresponding interrupt request, which is unmas k ed and w aits for the interrupt to be serviced, has the highest prior ity .
S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-15 INTPND Bit Description Init ial State INT_ADC [31] 0 = Not requested, 1 = Reques ted 0 INT_RT C [30] 0 = Not reques ted, 1 = Requested 0 INT_SP.
INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-16 INTERRUPT OFFSET (INT OFFSET) REGIST ER The value in the interr upt off set register shows which interrupt r equest of IRQ m ode is in the INTPND register. This bit can be cleared autom atically by clear ing SRCPND and INTPND.
S3C2440A RISC MICROPROCESSO R INTERRUPT CONTROLLER 14-17 SUB SOURCE PENDING (SUBSRCPND) REGISTER You can clear a specif ic bit of the SUBSRCPND regis ter by writing a data to this register. It clears only the bit positions of the SUBSRCPND regis ter corr esponding to those set to one in the data.
INTERRUPT CONTROLLER S3C2440A RISC MICROPROCESSOR 14-18 INTERRUPT SUB MASK (INTSUBM SK) REGISTER This register has 11 bits each of which is related to an interr upt sourc e.
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-1 15 LCD CONTROLLER OVERVIEW The LCD controller in the S3C2440A consists of the logic for tr ansfer ring LCD im age data from a video buf fer located in system m em ory to an external LCD driver.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-2 COMM ON FEATURES The LCD c ontroller has a dedic ated DMA that supports to f etch the im age data fr om video buf fer located in system mem or y . Its features also include: — Dedicated interr upt functions (INT_F rSy n and INT_FiCnt) — T he system m em ory is used as the display mem ory.
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-3 BLOCK DIA GRAM System Bus LPC3600 is a t im ing cont rol logic uni t for LTS 350Q1-PD1 or LTS350Q1-P D2.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-4 STN LCD CONTROLLER OPERATION TIM ING GENERA T OR (T IMEGEN) The TIMEG EN generates the c ontrol signals for the LCD dr iver, such as VF RAME, VLINE, VCLK, and VM. These control signals are c losely related to the configuration on the LCDCON1/2/3/4/5 registers in the REGBANK.
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-5 Table 15- 1. Relation betw een VCLK an d CLKVAL (STN, HCLK=60M Hz) CLKVA L 60M Hz/X VCLK 2 60 MHz/4 15.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-6 256 Level Colo r Mo de Operatio n The S3C2440A LCD controller can support an 8-bit per pixel 256 color display m ode. The color display m ode can generate 256 levels of color using the dithering algorithm and FRC.
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-7 DITHERING AND FRA M E RATE CONTROL In case of STN LCD display ( except m onochrom e) , video data mus t be proces sed by a dithering algorithm.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-8 Display Types The LCD controller supports 3 types of LCD drivers : 4-bit dual s c an, 4-bit s ingle sc an, and 8- bit single s can dis play mode.
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-9 MEM ORY DATA FORM A T (ST N, BSWP=0) Mono 4-bit Dual Scan Display: Video Buff er Mem ory: Address Data 0000H A[31:0] 0004H B[31:0] • • • 1000H L.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-10 MEM ORY DATA FORM A T ( ST N, BSWP=0 ) (CONTINUED) In 4-level gray mode , 2 bits of video data cor respond to 1 pixel.
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-11 16 BPP Color mode 16 bits (5 bits of red, 6 bits of green, 5 bits of blue) of video data cor respond to 1 pixel. But, stn contr oller will use only 12 bit c olor data. It means that only upper 4bit each c olor data will be used as pix el data ( R[15:12], G[10:7], B[4:1]).
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-12 4-bit Dual Scan Display 4-bit Single Scan Display 8-bit Single Scan Display . . . . . . . . . . . . VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 . . .
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-13 VD3 R1 VD2 G1 VD1 B1 VD0 R2 VD3 G2 VD2 B2 VD1 R3 VD0 G3 . . . . . . 1 Pixel . . . . . . 4-bit Dual Scan Display VD3 R1 VD2 G1 VD1 B1 VD0 R2 VD3 G2 VD2 B2 VD1 R3 VD0 G3 . . . . . . 1 Pixel 4-bit Single Scan Display VD7 R1 VD6 G1 VD5 B1 VD4 R2 VD7 G2 VD6 B2 VD5 R3 VD4 G3 .
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-14 Timing Requirements Image data s hould be transf erred f rom the m emor y to the LCD dr iver using the VD[7:0] signal. VCLK signal is used to clock the data into the LCD dr iver's shif t register .
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-15 WDLY WLH LINE1 LINE2 LINE3 LINE4 LINE5 LINE6 LINE1 LINEn First Line Timing LINECNT decreases & Display the 1st line LINEBLANK First Line Check &a.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-16 TFT LCD CONTROLLER OPERA TION The T IMEGEN generates the control signals f or LCD driver, s uch as VSYNC, HSYNC, VCLK, VDEN, and LEND signal. These control signals are highly related with the configurations on the LCDCON1/2/3/4/5 registers in the REGBANK.
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-17 MEM ORY DATA FORM A T (TFT ) This section inc ludes som e exam ples of each display mode. 24BPP Display (BSW P = 0, HW SW P = 0, BPP24BL = 0) D[31:24] D[23: 0] 000H Dumm y Bit P1 004H Dumm y Bit P2 008H Dumm y Bit P3 .
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-18 16BPP Display (BSW P = 0, HW SW P = 0) D[31:16] D[15: 0] 000H P1 P2 004H P3 P4 008H P5 P6 ... (BSW P = 0, HW SW P = 1) D[31:16] D[ 15:0] 000H P2 P1 004H P4 P3 008H P6 P5 .
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-19 8BPP Display (BSW P = 0, HW SW P = 0) D[31:24] D[ 23:16] D[ 15:8] D[7:0] 000H P1 P2 P3 P4 004H P5 P6 P7 P8 008H P9 P10 P11 P12 ... (BSW P = 1, HW SW P = 0) D[31:24] D[ 23:16] D[ 15:8] D[7:0] 000H P4 P3 P2 P1 004H P8 P7 P6 P5 008H P12 P11 P10 P9 .
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-20 4BPP Display (BSW P = 0, HW SW P = 0) D[31: 28] D[27:24] D[ 23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H P1 P2 P3 P4 P5 P6 P7 P8 004H P9 P10 P11 P12 P13 P14 P15 P16 008H P17 P18 P19 P20 P21 P22 P23 P24 .
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-21 256 PA L ETT E USA G E (T FT) Palette Configur ation and Format Control The S3C2440A provides 256 color palette f or T FT LCD Contr ol. The us er can selec t 256 colors f rom the 64K colors in these two form ats.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-22 12345 LCD Panel 16BPP 5:5:5+1 Format(Non-Palette) A[31] A[30] A[29] A[28] A[27] A[26]A[25] A[24] A[23] A[22] A[21] A[20] A[19]A[18] A[17] A[16] R4 R3 .
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-23 INT_FrSyn VSYNC HSYNC VDEN HSYNC VCLK VD LEND VBPD+1 VSPW+1 VFPD+1 HBPD+1 HFPD+1 HSPW+1 VDEN 1 Frame 1 Line LINEVAL +1 HOZVAL+1 Figure 15-6.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-24 SA M SUNG T FT LCD PA NEL (3.5” PORT RA IT / 256K COLO R / REFLECTIVE A-SI/TRANSFLECTIVE A - SI TFT LCD) The S3C2440A s upports following SEC T FT LCD panels . 1. SAMSUNG 3.5” Portr ait / 256K Color /Reflec tive a-Si TF T LCD.
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-25 VIRTUAL DISPLA Y (TFT /STN) The S3C2440A s upports hardware horizontal or vertic al scrolling. If the sc reen is sc rolled, the fields of LCDBASEU and LCDBASEL in LCDSADDR1/2 registers need to be changed (see F igure 15-8), exc ept the values of PAGEW IDTH and O FFSIZE.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-26 LCD POWER ENA BLE (ST N/TFT ) The S3C2440A provides Power enable ( PW REN) f unc tion. W hen PW REN is s et to m ak e PW REN s ignal enabled, the output value of LCD_PW REN pin is controlled by ENVID.
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-27 LCD CONT ROLLER SPECIAL REGISTERS LCD Control 1 Register Register Address R/W Description Reset Valu e LCDCON1 0X4D000000 R/W LCD control 1 regis ter 0x00000000 LCDCON1 Bit Description Initial State LINECNT (read only) [27:18] Pr ovide the status of the line counter.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-28 LCD Control 2 Register Register Address R/W Description Reset Valu e LCDCON2 0X4D000004 R/W LCD control 2 register 0x00000000 LCDCON2 Bit Description .
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-29 LCD Control 3 Register Register Address R/W Description Reset Valu e LCDCON3 0X4D000008 R/W LCD control 3 regis ter 0x00000000 LCDCON3 Bit Descriptio.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-30 LCD Control 4 Register Register Address R/W Description Reset Valu e LCDCON4 0X4D00000C R/W LCD c ontrol 4 register 0x00000000 LCDCON4 Bit Description Initial state MVAL [15:8] STN : T hese bit def ine the rate at which the VM signal will toggle if the MMODE bit is set to logic '1'.
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-31 LCD Control 5 Register Register Address R/W Description Reset Valu e LCDCON5 0X4D000010 R/W LCD control 5 regis ter 0x00000000 LCDCON5 Bit Description Initial state Reserved [31:17] T his bit is res erved and the value should be ‘0’.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-32 LCD Control 5 Register (Continue d) LCDCON5 Bit Description Initial state INVVDEN [6] TFT : This bit indicates the VDEN signal polarity. 0 = normal 1 = inverted 0 INVPW REN [5] STN/T FT : This bit indicates the PW REN signal polar ity .
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-33 FRAME BUFFER ST A RT ADDRESS 1 REGISTER Register Address R/W Description Reset Valu e LCDSADDR1 0X4D000014 R/W ST N/TF T : Fr am e buffer start addre.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-34 FRAME Buffer St art A d dress 3 Register Register Address R/W Description Reset Valu e LCDSADDR3 0X4D00001C R/W STN/T FT : Virtual sc reen address set 0x00000000 LCDSA DDR3 Bit Description Initial State OFFSIZE [21:11] Virtual screen of fset s ize (the number of half words) .
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-35 RED Lookup Table Register Register Address R/W Description Reset Valu e REDLUT 0X 4D000020 R/W STN : Red look up table regis ter 0x00000000 REDLUT Bit Description Initial State REDVAL [31:0] Thes e bits define which of the 16 shades will be chos en by eac h of the 8 possible red c ombinations .
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-36 Dithering Mode Register Register A ddress R/W Descriptio n Reset Value DITHMO DE 0X4D00004C R/W ST N : Dithering m ode regist er. This register r eset value is 0x 00000 But, user can change this value to 0x12210.
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-37 Temp Palette Register Register A ddress R/W Descriptio n Reset Value TPAL 0X 4D000050 R/W TFT : Tem porary palette register. This register value will be video data at next f ram e. 0x 00000000 TPAL Bit Descriptio n Initial state TPALEN [24] Tem porary palette register enable bit.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-38 LCD Interrupt Pe nding Register Register A ddress R/W Descriptio n Reset Value LCDINTPND 0X 4D000054 R/W Indic ate the LCD interrupt pending regis ter 0x 0 LCDINTPND Bit Description In itial state INT_FrSyn [1] LCD fram e synchronized interrupt pending bit.
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-39 LCD Interrupt M ask Register Register A ddress R/W Descriptio n Reset Value LCDINTMSK 0X 4D00005C R/W Determ ine which interrupt sour ce is m ask ed. The m ask ed interr upt source will not be ser viced.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-40 TCON Control Register Register A ddress R/W Descriptio n Reset Value TCO NSEL 0X4D000060 R/W This register c ontrols the LPC3600/LCC3600 modes .
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-41 Register S etting Guide (STN) The LCD c ontroller supports m ultiple screen s izes by spec ial register setting. The CLKVAL value determines the frequency of VCLK. T his value has to be determ ined s uch that the VCLK value is greater than data tr ansmission r ate.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-42 Example 1: 160 x 160, 4-level gray, 80 fram e/sec , 4-bit single sc an display, HCLK frequency is 60 MHz W LH = 1, W DLY = 1.
S3C2440A RISC MICROPROCESSO R LCD CONTROLLER 15-43 Gray Level Selection Guide The S3C2440A LCD controller can gener ate 16 gray level using Fram e Rate Control (FRC) . The FRC character istics m ay cause unexpected patterns in gr ay level. Thes e unwanted erroneous patterns m ay be shown in fast r esponse LCD or at lower f ram e rates.
LCD CONTROLLER S3C2440A RISC MICROPROCESSOR 15-44 Register Se tting Guide (T FT LCD) The CLKVAL regis ter value determ ines the f requency of VCLK and fram e rate.
S3C2440A RISC MICROPROCESSOR A DC AND TOUCH SCREEN INTERFACE 16-1 16 A DC & TOUCH SCREEN INTERFA CE OVERVIEW The 10-bit CMOS ADC (Analog to Digital Converter) is a rec ycling ty pe device with 8-channel analog inputs . It converts the analog input signal into 10-bit binary digital codes at a max imum c onversion rate of 500KSPS with 2.
ADC A ND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR 16-2 A DC & TOUCH SCREE N INTERFA CE OP E RA TION BLOCK DIA GRAM Figure 16-1 shows the f unctional block diagram of A/D converter and T ouch Scr een Interfac e. Note that the A/D converter devic e is a rec y c ling type.
S3C2440A RISC MICROPROCESSOR A DC AND TOUCH SCREEN INTERFACE 16-3 FUNCTION DESCRIPTIONS A /D Conversion Time W hen the GCLK fr equency is 50MHz and the pr escaler value is 49, total 10-bit conver sion tim e is as f ollows.
ADC A ND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR 16-4 Programming Note s 1. T he A/D converted data can be access ed by m eans of interrupt or polling m ethod.
S3C2440A RISC MICROPROCESSOR A DC AND TOUCH SCREEN INTERFACE 16-5 A DC AND TOUCH SCREEN INTERFA CE SPECI A L REGI STERS A DC CONT ROL REGISTER (ADCCON) Register Address R/W Description Reset Value ADC.
ADC A ND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR 16-6 A DC T OUCH SCREEN CONTROL REGIST ER (A DCTSC) Register Address R/W Description Reset Value ADCTSC 0x5800004 R/W ADC T ouch Scr een Control Register 0x58 A DCT SC Bit Description In itial St ate UD_SEN [8] Detect Stylus Up or Down status.
S3C2440A RISC MICROPROCESSOR A DC AND TOUCH SCREEN INTERFACE 16-7 A DC ST A RT DELA Y REGISTER (ADCDLY) Register Address R/W Description Reset Value ADCDLY 0x5800008 R/W ADC Start or Interval Delay Regis ter 0x00ff A DCDLY Bit Description Initial State DELAY [15:0] 1) Nor m al Conversion Mode, XY Position Mode, Auto Position Mode.
ADC A ND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR 16-8 A DC CONVERSION DATA REGIST ER (A DCDAT0) Register Address R/W Description Reset Value ADCDAT0 0x580000C R ADC Conversion Data Register - A DCDAT0 Bit Description Initial State UPDOW N [15] Up or Down state of Stylus at W aiting f or Interrupt Mode.
S3C2440A RISC MICROPROCESSOR A DC AND TOUCH SCREEN INTERFACE 16-9 A DC CONVERSION DATA REGIST ER (A DCDAT1) Register Address R/W Description Reset Value ADCDAT1 0x5800010 R ADC Conversion Data Register - A DCDAT1 Bit Description Initial State UPDOW N [15] Up or Down state of Stylus at W aiting f or Interrupt Mode.
ADC A ND TOUCH SCREEN INTERFACE S3C2440A RISC MICROPROCESSOR 16-10 NOT ES.
S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK 17-1 17 REA L TIME CLOCK OVERVIEW The Real T im e Clock (RT C) unit can be operated by the backup batter y while the system power is off. T he RT C can transm it 8-bit data to CPU as Binary Coded Decimal (BCD) values us ing the ST RB/LDRB ARM operation.
REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR 17-2 REA L T IM E CLOCK OPERA TION 2 15 Clock Divider XTOrtc XTIrtc Control Register SEC MIN HOUR DAY DATE MON YEAR Leap Year Generator Alarm Gene r ator Reset Register 1 Hz INT_RTC RTCCON RTCA LM RTCRST Time Tick Generat or TIME TICK TICNT 128 Hz PMW KUP Figure 17-1.
S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK 17-3 A LARM FUNCTION The RT C generates an alar m s ignal at a specif ied tim e in the power-off mode or norm al operation m ode. In nor m al operation m ode, the alarm inter rupt ( INT_RT C) is ac tivated.
REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR 17-4 REA L TIME CLOCK SPECIA L REGISTERS REA L T IM E CLOCK CONTROL (RTCCON) REGIST ER The RT CCON regis ter consis ts of 4 bits such as the RT CEN, which controls the read/write enable of the BCD registers , CLKSEL, CNTSEL, and CLKRST for testing.
S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK 17-5 RTC ALA RM CONT ROL (RTCALM) REGIST ER The RT CALM register determ ines the alarm enable and the alarm tim e. Please note that the RTCALM register generates the alarm signal through both INT _RT C and PMW KUP in power down m ode, but only through INT _RT C in the norm al operation m ode.
REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR 17-6 A LARM SECOND DATA (A L MSEC) REGIST ER Register Address R/W Descript ion Reset Valu e ALMSEC 0x57000054(L) 0x57000057(B) R/W (by byte ) Alarm second data r egister 0x0 A LM SEC Bit Description Initial State Reserved [7] 0 SECDATA [6:4] BCD value for alarm second.
S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK 17-7 A LARM DA T E DA T A (ALMDA T E) REGISTER Register Address R/W Description Reset Valu e ALMDATE 0x 57000060(L) 0x57000063(B) R/W (by byte ) Alarm date data register 0x 01 A LM DATE Bit Descrip tion Initial Stat e Reserved [7:6] 00 DATEDAT A [5:4] BCD value for alarm date, f rom 0 to 28, 29, 30, 31.
REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR 17-8 BCD SECOND (BCDSEC) REGISTER Register Address R/W Description Reset Value BCDSEC 0x57000070(L) 0x57000073(B) R/W (by byte ) BCD s econd register Undef ined BCDSEC Bit Description In itial Stat e SECDATA [6:4] BCD value f or sec ond.
S3C2440A RISC MICROPROCESSOR REAL TIME CLOCK 17-9 BCD DA T E (BCDDA T E) REGISTER Register Address R/W Description Reset Valu e BCDDATE 0x5700007C(L) 0x5700007F(B) R/W (by byte ) BCD date regis ter Undef ined BCDDA T E Bit Description Initial State Reserved [7:6] - DATEDAT A [5:4] BCD value for date.
REAL TIME CLOCK S3C2440A RISC MICROPROCESSOR 17-10 BCD YEA R (BCDY EA R) REGIST ER Register Address R/W Descriptio n Reset Valu e BCDYEAR 0x57000088(L) 0x5700008B(B) R/W (by byte ) BCD year register Undef ined BCDYEA R Bit Description Initial State YEARDATA [7:0] BCD value for year.
S3C2440A RISC MICROPROCESSOR WATCHDOG TIMER 18-1 18 WA TCHDOG TIMER OVERVIEW The S3C2440A watchdog tim er is us ed to res um e the c ontroller operation whenever it is dis turbed by m alf unctions such as nois e and system error s. It can be used as a normal 16- bit interval tim er to request interrupt s ervice.
WATCHDOG TIMER S3C2440A RISC MICROPROCESSOR 18-2 WA T CHDOG TIM ER OPERA T ION Figure 18-1 shows the functional block diagram of the watchdog tim er. The watchdog tim er us es only PCLK as its source c lock . The PCLK f requency is prescaled to generate the c orresponding watchdog timer clock, and the resulting f requency is divided again.
S3C2440A RISC MICROPROCESSOR WATCHDOG TIMER 18-3 WA TCHDOG TIMER SPECIA L REGISTERS WA T CHDOG TIM ER CONTROL (W TCON) REGISTER The W T CON regis ter allows the user to enable/disable the watchdog tim er, s elect the cloc k signal fr om 4 diff erent sources , enable/disable interrupts, and enable/disable the w atchdog tim er output.
WATCHDOG TIMER S3C2440A RISC MICROPROCESSOR 18-4 WA T CHDOG TIM ER DA TA (WTDA T ) REGISTER The W TDAT register is us ed to specif y the tim e- out duration. The c ontent of W T DAT c annot be autom atically loaded into the tim er counter at initial watchdog tim er operation.
S3C2440A RISC MICROPROCESSO R MM C/SD/SDIO CONTROLLER 19-1 19 MMC/SD/SDIO Controller FEA TURES SD Memor y Car d Spec(ver 1.0) / MMC Spec (2.11) com patible SDIO Card Spec( Ver 1.
MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-2 SD OPERA TION A serial cloc k line s y nc hronizes shif ting and sam pling of the inf orm ation on the f ive data lines . T he trans m ission frequenc y is c ontrolled by making the appropr iate bit settings to the SDIPRE regis ter.
S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER 19-3 SDIO OPERA TION There are two functions of SDIO oper ation: SDIO Inter rupt r ec eiving and Read W ait Request generation. T hese two functions can operate w hen RcvIO Int bit and RwaitEn bit of SDICON register is activated res pectively.
MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-4 SDI SPECIA L REGISTERS SDI Control Register(SDICON) Register Address R/W Description Reset Value SDICON 0x5A000000 R/W SDI Control Register 0x0 SDICON Bit Descript ion Initial Value Reserved [31:9] SDMMC Reset (SDreset) [8] Reset whole sdm m c bloc k.
S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER 19-5 SDI Command A rgument Register(S DICmdArg) Register Address R/W Description Reset Value SDICmdAr g 0x5A000008 R/W SDI Comm and Argum ent Regis .
MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-6 SDI Command Status Re gister(SDICmdSta) Register Address R/W Description Reset Value SDICmdSta 0x 5A000010 R/(C) SDI Com m and Status Regis ter 0x0 SDICmdSta Bit Descripti on Initial Value Reserved [31:13] Response CRC Fail(Rsp Crc) [12] R/C CRC check failed when com m and respons e received.
S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER 19-7 SDI Response Regist er 2(SDIRSP2) Register Address R/W Description Reset Value SDIRSP2 0x5A00001C R SDI Respons e Register 2 0x0 SDIRSP2 Bit De.
MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-8 SDI Data Control Register(SDIDatCon) Register Address R/W Description Reset Value SDIDatCon 0x5A00002C R/W SDI Data control Register 0x0 SDIDatCon Bit Description Init ial Value Reserved [31:25] Burst4 enable (Burst4) [24] Enable Bur st4 m ode in DMA m ode.
S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER 19-9 SDI Data Remain Counte r Register(S DIDa tCnt) Register Address R/W Description Reset Value SDIDatCnt 0x5A000030 R SDI Data Rem ain Counter Reg.
MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-10 SDI FIFO Status Registe r(SDIFSTA ) Register Address R/W Description Reset Value SDIFSTA 0x5A000038 R/(C) SDI FIFO Status Register 0x0 SDIFSTA Bit Description Initial State Reserved [31:16] FIFO Reset(FRST) [16] C Reset FIF O value.
S3C2440A RISC MICROPROCESSOR MMC/SD/SDIO CONTROLLER 19-11 SDI Interrupt Mask Reg ister(SDIIntM sk) Register Address R/W Description Reset Value SDIIntMsk 0x5A00003C R/W SDI Interrupt Mas k Regis ter 0.
MMC/SD/SDIO CONTROLLER S3C2440A RISC MICROPROCESSOR 19-12 SDI Data Register(SDIDA T ) Register Address R/W Descriptio n Reset Value SDIDAT 0x5A000040, 44, 48, 4C(Li/W , Li/HW , Li/B, Bi/W ) 0x5A000041.
S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE 20-1 20 IIC-BUS INTERFA CE OVERVIEW The S3C2440A RISC m icr oprocess or can suppor t a multi- m aster IIC-bus serial interf ace. A dedicated serial data line (SDA) and a ser ial clock line (SCL) car ry inform ation between bus m as ters and peripher al devices which ar e connected to the IIC-bus .
IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-2 PCLK Address Register SDA 4-bit Prescaler IIC-Bus Control Logic IICSTAT IICCON Comparator Shift Register Shift Register (IICDS) Data Bus SCL Figure 20-1.
S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE 20-3 IIC-BUS INTERFACE The S3C2440A IIC-bus interfac e has four operation m odes: — Master tr ansm itter m ode — Master receive m ode — Slave transm itter m ode — Slave rec eive mode Functional relations hips am ong these operating m odes ar e described below.
IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-4 DA TA TRA NS FER FOR MA T Every by te placed on the SDA line should be eight bits in length. The bytes can be unlim itedly transmitted per transf er. T he f irst by te f ollowing a Start condition s hould have the address f ield.
S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE 20-5 SDA Acknowledgement Signal from Receiver SCL S 1 27 8 9 1 2 9 Acknowledgement Signal from Receiver MSB ACK Byte C omplete, Inter rupt within Receiver Clock Line Held Low by receiver and/or transm itter Figure 20-4.
IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-6 REA D-WRIT E OPERA T ION In Trans m itter m ode, when the data is transfer red, the IIC-bus inter face will wait until IIC-bus Data Shift ( IICDS) register rec eives a new data.
S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE 20-7 FLOWCHA RT S OF OPERATIONS IN EA CH M ODE The f ollowing steps m ust be exec uted before any IIC Tx/Rx oper ations. 1) W rite own slave address on IICADD register, if needed. 2) Set IICCON regist er.
IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-8 Write slave address to IICDS. Write 0xB0 (M/R Start) to IICSTAT. The data of the IICDS (slave address) is transmitted. ACK period and then interrupt is pending. Write 0x90 (M/R Stop) to IICSTAT. Read a new data from IICDS.
S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE 20-9 IIC detects s tart signal. and, IICDS receives data. IIC com pares IICADD and IICDS ( the received s lave address ). W r ite data to IICDS. The IIC addres s m atch interrupt is gener ated. Clear pending bit to resume.
IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-10 IIC detects s tart signal. and, IICDS receives data. IIC com pares IICADD and IICDS ( the received s lave address ). Read data from IICDS. The IIC addres s m atch interrupt is gener ated. Clear pending bit to resume.
S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE 20-11 IIC-BUS INTER FAC E SPECIAL R EGISTERS MULT I-M A ST ER IIC-BUS CONTROL (IICCON) REGIST ER Register Address R/W Descriptio n Reset Value IICCON 0x54000000 R/W IIC-Bus control r egister 0x0X IICCON Bit Description Initial St ate Ack nowledge generation (1) [7] IIC-bus ack nowledge enable bit.
IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-12 MULT I-M A ST ER IIC-BUS CONT ROL/STATUS (IICSTA T) REGISTER Register Address R/W Descriptio n Reset Value IICSTAT 0x 54000004 R/W IIC-Bus contr ol/status regis ter 0x0 IICSTAT Bit Description Initial State Mode selection [7:6] IIC-bus m aster /slave T x/Rx m ode select bits.
S3C2440A RISC MICROPROCESSOR IIC-BUS INTERFACE 20-13 MU LTI- MASTER IIC-BUS ADDRESS (IICA DD) REGIST ER Register Address R/W Descriptio n Reset Value IICADD 0x54000008 R/W IIC- Bus address r egister 0x XX IICA DD Bit Description In itial St ate Slave address [7:0] 7-bit slave addres s, latched f rom the IIC-bus.
IIC-BUS INTERFACE S3C2440A RISC MICROPROCESSOR 20-14 MULT I-M A ST ER IIC-BUS LINE CONTROL(IICLC) REGIST ER Register Address R/W Descriptio n Reset Value IICLC 0x54000010 R/W IIC-Bus m ulti-m aster line control regis ter 0x00 IICLC Bit Descript ion Initial St ate Filter Enable [2] IIC-bus filter enable bit.
S3C2440A RISC MICROPROCESSO R IIS-BUS INTERFACE 21-1 21 IIS-BUS INTERFA CE OVERVIEW Currently , m any di gital audio sy stem s are attracting the consumers on the m ark et, in the form of com pact discs, digital audio tapes , digital sound pr ocessor s, and digital T V sound.
IIS-BUS INTERFACE S3C2440A RISC MICROPRO CESSOR 21-2 BLOCK DIA GRAM ADDR DAT A CNTL PCLK BRFC I PSR_A I PSR_B TxFI FO RxFI FO SCLKG CHNC SFTR L RCK SCLK SD CDCL K MP LL i n Figure 21-1.
S3C2440A RISC MICROPROCESSO R IIS-BUS INTERFACE 21-3 D M A T R AN S F E R In this m ode, transm it or rec eive FIFO is acces sible by the DMA controller. DMA service r equest in transm it or receive m ode is m ade by the FIFO ready flag automatic ally.
IIS-BUS INTERFACE S3C2440A RISC MICROPRO CESSOR 21-4 IIS-bus Format (N=8 or 16) MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) LRCK SCLK SD LEFT RIGHT LEFT MSB-justified Format (N=8 or 16) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) LRCK SCLK SD LEFT RIGHT MSB (1st) Figure 21-2.
S3C2440A RISC MICROPROCESSO R IIS-BUS INTERFACE 21-5 IIS-BUS INTERF ACE SPEC IAL REGISTERS IIS CONTROL (IISCON) REGIST ER Register Address R/W Description Reset Value IISCON 0x55000000 (Li/HW , Li/W ,.
IIS-BUS INTERFACE S3C2440A RISC MICROPRO CESSOR 21-6 IIS MO DE REGIST ER (IISMO D) REGIST ER Register Address R/W Description Reset Value IISMOD 0x 55000004 (Li/W , Li/HW , Bi/W ) 0x55000006 (Bi/HW ) .
S3C2440A RISC MICROPROCESSO R IIS-BUS INTERFACE 21-7 IIS PRESCA LER ( IISPSR) REGIST ER Register Address R/W Description Reset Value IISPSR 0x55000008 ( Li/HW , Li/W , Bi/W ) 0x5500000A (Bi/HW ) R/W I.
IIS-BUS INTERFACE S3C2440A RISC MICROPRO CESSOR 21-8 IIS FIFO CONT ROL (IISFCON) REGIST ER Register Address R/W Descriptio n Reset Value IISFCON 0x 5500000C (Li/HW , Li/W , Bi/W ) 0x5500000E (Bi/HW ) .
S3C2440A RISC MICROPROCESSOR SPI 22-1 22 SPI OVERVIEW The S3C2440A Serial Per ipheral Interfac e (SPI) can inter face with the ser ial data transfer . T he S3C2440A includes two SPI, eac h of which has two 8-bit shift regis ters f or trans mis sion and receiving, r espectively.
SPI S3C2440A RISC MICROPROCESSOR 22-2 BLOCK DIA GRAM 8bit Prescaler 1 PCLK Status Register 1 Prescaler Register 1 /SS nSS 0 SCK SPICLK 0 MOSI SPIMOSI 0 MISO SPIMISO 0 Pin Control Logic 0 MSTR Tx 8bit .
S3C2440A RISC MICROPROCESSOR SPI 22-3 SPI OPERA TION Using the SPI interf ace, S3C2440A can s end/receive 8-bit data s imultaneous ly with an external device. A serial clock line is synchronized with the tw o data lines for shifting and s am pling of the inf orm ation.
SPI S3C2440A RISC MICROPROCESSOR 22-4 SPI TRANSFER FORM A T The S3C2440A s upports 4 diff erent f orm ats to transf er data. Figure 22- 2 shows the four wavef orm s for SPICLK.
S3C2440A RISC MICROPROCESSOR SPI 22-5 TRANSMITT ING PROCEDURE FOR DM A 1. SPI is conf igured as DMA m ode. 2. DMA is conf igured properly. 3. SPI r equests DMA s ervice. 4. DMA tr ansm its 1byte data to the SPI. 5. SPI tr ansm its the data to card. 6.
SPI S3C2440A RISC MICROPROCESSOR 22-6 SPI SPECIA L REGISTERS SPI CONTROL REGIST ER Register Address R/W Description Reset Value SPCON0 0x 59000000 R/W SPI channel 0 c ontrol register 0x00 SPCON1 0x 59.
S3C2440A RISC MICROPROCESSOR SPI 22-7 SPI STATUS REGIST ER Register Address R/W Description Reset Value SPSTA0 0x59000004 R SPI c hannel 0 status r egister 0x01 SPSTA1 0x59000024 R SPI c hannel 1 stat.
SPI S3C2440A RISC MICROPROCESSOR 22-8 The SPIMISO (MISO) and SPIMOSI ( MOSI) data pins ar e used for transm itting and r eceiving s erial data. W hen SPI is conf igured as a m aster , SPIMISO (MISO ) is the m aster data input line, SPIMOSI (MOSI) is the m aster data output line, and SPICLK (SCK) is the clock output line.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-1 23 CA MERA INTERFA CE OVERVIEW This chapter will explain the specif ication and def ines the c am era inter f ac e. CAMIF (C A Mera In terFace ) wi thin the S3C2440A consists of 7 parts – pattern mux, capturin g unit, p review scaler, codec scaler, preview DMA, codec DMA , and SFR .
S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-2 BLOCK DIA GRAM YCbCr 4:2:2 T_patternMux CatchCam YCbCr 4:2:X Preview Scaler & RGB Formatter Codec Scaler Prev iew D MA ITU -R BT 601/656 Codec D.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-3 TIM ING DIA GRAM jht}zuj jht}zuj jht}zuj jht}zuj j j j j j jhtoylm jhtoylm jhtoylm jhtoylm jhtoylmG j.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-4 Table 23- 2 Video T iming Reference Cod es of IT U-656 Format Data bit number First word Second word T hird word Fourth word 9 (MSB) 1 0 0 1 8 1 0 0.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-5 CA MERA INTERFA CE OPERA TION TWO D M A PA THS CAMIF has 2 DMA paths. P-path (Previe w path) and C-path (Codec path) are separated f rom each other on th e AHB bus. In view of the system bus, both the paths are independent.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-6 m al-func tioning CAMCLKOUT Divide Counter 1/1 ~ 1/16 UPLL Extern al Camera Processor CAMPCLK S3C2440A CA M IF USB PLL 96 MHz f USB /d f USB MPL L Variable Freq.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-7 ME MOR Y S TORI NG METH OD The little-endian m ethod in c odec path is us ed to store in the f ram e m emor y . T he pixels are stored fr om LSB to MSB side. AHB bus carries 32-bit word data. So, CAMIF mak es eac h of the Y-Cb-Cr words in little-endian style.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-8 TIM ING DIA G RA M FOR REGIST ER SETT ING The f irst regis ter setting f or fr ame c apture com m and can occ ur anyw here in the fr ame per iod.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-9 TIM ING DIA GRAM FOR LA ST IRQ IRQ except Las tIRQ is generated bef ore im age capturing. Las t IRQ which m eans captur e-end can be set by following tim ing diagram. Las tIRQEn is auto-c leared and ,as m entioned, SFR setting in ISR is for nex t fram e com m and.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-10 CA MERA INTERFA CE SPECIA L REGISTERS SOURCE FORMAT REGISTER Register Address R/W Descrip tion Reset Value CISRCFMT 0x4F 000000 RW Input Sour ce Form at Register 0 CISRCFM T Bit Description Init ial State ITU601_656n [31] 0 = ITU-R BT .
S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-11 WINDOW OPTION REGIS T ER Register Address R/W Descrip tion Reset Value CIW DOFST 0x4F000004 RW W indow Offs et Register 0 CIWDOFST Bit Description .
S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-12 GLOBA L CONT ROL REGISTER Register Address R/W Descrip tion Reset Value CIGCT RL 0x4F000008 RW G lobal Control Register 0 CIGCT RL Bit Descript ion.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-13 Y3 ST A RT ADDRESS REGISTER Register Address R/W Descrip tion Reset Value CICOYSA3 0x4F000020 RW Y 3 rd fram e star t address f or codec DMA 0 CICO.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-14 CB4 START A DDRESS REG ISTER Register Address R/W Descrip tion Reset Value CICOCBSA4 0x4F000034 RW Cb 4 th fram e start addres s for c odec DMA 0 C.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-15 CODEC TARGET FORMAT REGISTER Register Address R/W Description Reset Value CICOTR GFMT 0x 4F000048 RW Target im age for mat of codec DMA 0 CICOTRG FM T Bit Descript ion Initial State In422_Co [31] 0 = YCbCr 4:2:0 codec s caler input im age f orm at.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-16 CODEC DMA CONTROL REGISTER Register Address R/W Description Reset Value CICOCTRL 0x4F00004C RW Codec DMA control related 0 CICOCTRL Bit Description.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-17 REGISTER SET T ING GUIDE FO R CODEC SCALER A ND PREVIEW SCA LER SRC_Width and DST_Width satisf y the w ord boundary constraints such that the num ber of hor izont al pixel can be represented to k n where n = 1,2,3, … and k = 1 / 2 / 8 for 24bppRGB / 16bppRGB / YCbCr420 im age, res pectively .
S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-18 If ( SRC_Height >= 64 × DST _Height ) { Ex it(-1); /* O ut Of V ertic al Scale Range */ } else if ( SRC_Height >= 32 × DST_Height) { PreV e.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-19 CODEC MAIN-SCA LER CONTROL REGIST ER Register Address R/W Descript ion Reset Value CICOSCCTRL 0x 4F000058 RW Codec m ain-scaler control 0 CICOSCCTR.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-20 CODEC STATUS REGISTER Register Address R/W Description Reset Value CICOSTAT US 0x4F000064 R Codec path s tatus 0 CICOSTATUS Bit Descrip tion Init i.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-21 RGB3 START ADDRESS REGISTER Register Address R/W Description Reset Value CIPRCLRSA3 0x4F000074 RW RG B 3 rd f ram e start addr ess f or preview DMA.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-22 PREVIEW DM A CO NTRO L REGIST ER Register Address R/W Descrip tion Reset Value CIPRCTRL 0x4F000080 RW Preview DMA control related 0 CIPRCTRL Bit De.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFA CE 23-23 PREVIEW PRE-SCALER CONTROL REG ISTER 2 Register Address R/W Descript ion Reset Value CIPRSCPREDST 0x4F000088 RW Preview pre-sc aler destination f o.
S3C2440A RISC MICROPROCESSOR CAMERA INTERFAC E 23-24 PREVIEW ST A T US REGIST ER Register Address R/W Descript ion Reset Valu e CIPRSTAT US 0x 4F000098 R Preview path status 0 CIPRSTATUS Bit Descripti.
S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER 24-1 24 A C97 CONTROLLER OVERVIEW The AC97 Controller Unit of the S3C2440A s upports AC97 revis ion 2.0 features . AC97 Controller com m unicates with AC97 Codec using an audio controller link (AC- link). Contr oller sends the s tereo PCM data to Codec .
AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-2 A C97 CONTROLLE R OP E RA TION BLOCK DIA GRAM Figure 24-1 shows the f unctional block diagram of the S3C2440A AC97 Controller. T he AC97 signals for m the AC- link, which is a point-to-point s y nc hronous s erial interconnec t that supports f ull-duplex data tr ansfer s.
S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER 24-3 IN TERN A L DA TA PA TH Figure 24-2 shows the internal data path of the S3C2440A AC97 Controller . It has ster eo Pulse Code Modulated (PCM) In, Stereo PCM O ut and m ono Mic-in buf fers, which consis t of 16-bit, 16 entries buf fer.
AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-4 OPERA TION FLOW CHA RT Syst em r eset o r Co ld r eset Set GPIO an d Release INTM SK/SU BINTM SK bits Enable Codec Ready interrupt Codec Re ady inter .
S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER 24-5 A C-LINK DIGITA L INTERFAC E PROTOCOL Each AC97 Codec inc orpor ates a f ive-pin digital ser ial interf ac e that link s it to the S3C2440A AC97 Contr oller. T he AC-link is a full- duplex, fix ed-clock , PCM digital st ream .
AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-6 A C-LINK INPUT FRA M E (SDATA _IN) S D AT A_ O U T BIT_CLK SYNC AC '97 sam ples SYNC assertion her e AC '97 Controller samples fir s t SDATA.
S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER 24-7 Waking u p the AC-link - Wake Up T riggered by the AC97 Controller AC-link protocol is pr ovided for a c old AC97 reset and a warm AC97 reset. T he cur rent power-down state ultima tely dictates which AC97 r eset is used.
AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-8 A C97 CONTROLLER SPECIA L REGISTERS A C97 GLOBAL CONTROL REGISTER (A C_GLBCTRL) Register Address R/W Descrip tion Reset Valu e AC_GLBCTRL 0x5B000000 R.
S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER 24-9 A C97 GLOBA L STATUS REGIS TER (A C_GLBSTAT) Register Address R/W Description Reset Value AC_GLBST AT 0x5B000004 R AC97 Global Status Register 0x00000.
AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-10 A C97 CODEC ST A T US REGIST ER (A C_CODEC_ST A T ) Register Address R/W Description Reset Value AC_CODEC_ST AT 0x5B00000C R AC97 Codec Status Regist.
S3C2440A RISC MICROPROCESSOR AC97 CONTROLLER 24-11 A C97 M IC IN CHANNEL FIFO A DDRESS REGIST ER (AC_MICA DDR) Register Address R/W Description Reset Valu e AC_MICADDR 0x5B000014 R AC97 Mic In Channel.
AC97 CONTROLLER S3C2440A RISC MICROPROCESSOR 24-12 NOTES.
S3C2440A RISC MICROPROCESSOR BUS PRIORITIES 25-1 25 BUS PRIORITIES OVERVIEW The bus arbitration logic determ ines the priorities of bus m asters . It supports a c om bination of rotation priority mode and f ixed prior ity m ode. BUS PRIORITY MAP The S3C2440A holds 13 bus masters .
BUS PRIORITIES S3C2440A RISC MICROPROCESSOR 25-2 NOTES.
S3C2440A RISC MICROPROCESSOR MECHANICA L DATA 26-1 26 MECHA NICA L DA TA PA CKAGE DIMENSIONS 14.00 14.0 0 0.35 + 0.05 1.22 289-FBG A-1414 0.45 ±0.05 C 0.
MECHANICAL DA TA S3C2440A RISC MICROPROCESSOR 26-2 A1 INDEX MARK 0.80 x 16 = 12.8 0 ± 0.05 14.00 0.80 0.80 A B C D E F G H J K L M N P R T U 8 9 10 11 12 13 14 15 16 17 5 6 71 2 3 4 14.00 0.15 0.08 M M C C A B 289 - 0.45 ± 0.05 TOLERANCE ± 0.10 Figure 26-2 289- FBGA-1414 Package Dimension 2 (Bott om View) The rec om mended land open s ize is 0.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-1 27 ELECTRICA L DA TA A BSO LUTE MA XI MUM RA TING S Table 27-1 Absolute M aximum Rating Paramete r Symbol Rating Unit V DDi 1.2V V DD 1.8 V DDOP 3.3V V DD 4.8 V DDMOP 1.8V/2.5V/3.0V/3.3V V DD 4.8 V DDRTC 1.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-2 RECOMMENDED OPERATING CONDITIONS Table 27-2 Recommende d Operating Conditions Rating Parameter Symbol T yp. Min Max Unit DC Supply Voltage f or Alive Bloc k V DD alive 300MHz : 1.2V V DD 400MHz: 1.3V V DD 1.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-3 D.C. ELECTRICA L CHARA CTE RISTICS Table 27-3 and 27- 4 defines the DC elec trical char acteristic s for the standard LVCMOS I/O buff ers. Table 27- 3 Normal I/O PAD DC Electrical Characteristics Normal I/O PAD DC Electrical Characteristics for M emory (V DDMOP = 2.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-4 Normal I/O PAD DC Electrical Characteristics for M emory (V DDMOP =3.0V ± ± ± ± 0.3V, 3.3V ± ± ± ± 0.3V, T A =-40 to 85 ° ° ° ° C) Symbol P arameters Condition M in Typ. M ax Unit High level input voltage V IH LVCMOS interface 2.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-5 Normal I/O PAD DC Electrical Characteristics for I/O (V DDOP = 3.3V ± ± ± ± 0.3V, T A = -40 to 85 ° ° ° ° C) Symbol P arameters Condition M in Typ. M ax Unit High level input voltage V IH LVCMOS interface 2.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-6 Table 27- 4 USB DC Electrical Characteristics Symbol P arameter Condition M in M ax Unit V IH High level input voltage 2.5 V V IL Low level input voltage 0.8 V I IH High level input current Vin = 3.3V -10 10 µA I IL Low level input current Vin = 0.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-7 400M h z P o w er c o n su m p t io n 88m W 87m W 139m W 68m W 0 50 100 150 200 250 DVS( o) DV S( x ) Ite m Power[mW] Co r e P ow e r 104% Up Tota l P ow e r 46% Up Cor e P o w e r IO P o w e r 155mW 227mW Usi n g D VS w i thout D V S NOT E: (Condition) Current m eas ure condition: Play Battlife.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-8.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-9 A .C. ELE CTRICAL CHA RACTERISTICS 1/2 V DD 1/2 V DD t XTA L CY C NOTE: Clock input is from the X TI pll pin. Figure 27-2 XT Ipll Clock T iming Diagram t EXTHI GH V IH 1/2 V DD V IL V IL V IH V IH 1/2 V DD t EX TLOW t EX TCYC NOTE: Clock input is from the EX TCLK pin.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-10 HCLK (internal) SCLK CLKOUT (HCLK) t HC2CK t HC2SCLK Figure 27-5 HCLK/CL KOUT/SCLK in case when EXTCLK is used EXT CLK t RESW nRESET Figure 27-6 Man.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-11 nRESET XT Ipll or EXT CLK VCO output MCU o perates by XT Ipll or EXT CLK clcok. Clock Disable tPLL FCLK is new frequency . Pow er PLL can operate aft er OM[3:2] is la tched. PLL is configur ed by S/W first time.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-12 XTIpl l VCO Output Clock Disable FCLK Severa l slow clocks (X TIpll or EXT CLK ) Pow er_OFF mode is in itiated.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-13 HCLK nGCS x tRAD nOE DATA ADDR nBEx tRCD tROD tROD tRCD Tacc tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tR.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-14 HCLK nGCSx tRAD nOE DATA ADDR nBEx tRCD tROD tROD tRCD tRBED tRB ED Tacc tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRDS tRDH tRDS tRDH tRDS tRDH tRDS .
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-15 HCLK nGS nOE ADDR tXnBRQ S XnBREQ tXnBRQ H XnBACK 'HZ' 'HZ' 'HZ' tXnBACKD tXnBAC KD tHZD tHZD tHZD Figure 27-11 Extern.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-16 HCLK nGCSx tRAD Tacs nOE Tcos DATA ADDR nW BEx '1' Toc h Tc ah tRCD tROD tRDS tRDH tROD tRCD tRAD Tac c Figure 27-12 ROM /SRAM REA D Timin.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-17 HCLK nGCSx tRAD Tac s nOE Tcos DATA ADDR nBEx Toc h Tc ah tRCD tROD tRDS tRDH tROD tRCD tRAD tRBED tRBED Tac c Figure 27-13 ROM /SRAM REA D Timing D.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-18 HCLK nGCSx tRAD Tacs nWE Tcos DATA ADDR nWBEx Toch Tcah tRCD tRWD tRDD tRWD tRCD tRAD Tcos Toch tRWBED tRWBED Tacc tRDD Figure 27-14 ROM /SRAM WRIT .
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-19 HCLK nGCSx tRAD Tac s nW E Tco s DATA ADDR nBEx Toc h Tc ah tRCD tRW D tRDD tRW D tRCD tRAD tRBED tRBED Tac c tRDD Figure 27-15 ROM /SRAM WRIT E Tim.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-20 HCLK nGCSx nOE Tacc = 6c yc le nW ait DATA ADDR Tac s Tac s delayed tRC NOTE: The status of nW ait is checked at (Tacc-1) cy cle.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-21 HCLK nGCSx tRAD Tac s nOE Tc os DAT A ADDR tRCD tROD tRDS tRDH tRAD Tac c Figure 27-18 M asked- ROM Single READ Timing Diagram ( Tacs=2, T cos=2, T .
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-22 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/ BA nBEx tSRD tSD S tSDH SCKE A10/AP nGCSx tSCS D nWE tSAD tSCD tSWD '1' Trcd tSBED Tcl Figure 27-20 S.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-23 SCLK nSRAS nSCAS ADDR/BA nBEx tX nBR QH tXnBRQS SCKE A10/AP nGCSx nW E '1' XnBREQ Xn BA CK EXTCLK tXnBACKD tXnBAC KD 'HZ' '.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-24 SCLK nSRAS tSAD nSCAS DATA ADDR/BA nBEx tSRD SCKE A10/AP nGCSx tSCS D nW E tSAD tSCD tSW D '1' tSAD tSCSD tSRD 'HZ' '1&apos.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-25 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDS tSDH SCKE A10/AP nGCSx tSCSD nW E tSAD tSCD tSW D '1' tSAD tSAD Trcd tSCSD tSRD tSCS.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-26 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDS tSDH SCKE A10/AP nGCSx tSCSD nW E tSAD tSCD tSW D '1' tSAD tSAD Trc d tSCSD tSRD tSC.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-27 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD SCKE A10/AP nGCS x tSCSD nW E tSAD tSCD tSW D '1' tSAD tSCSD tSRD '1' '1' 'HZ' Trc NOTE: Before ex ecuting an auto/self refresh c o mmand, all the banks must be in idle state.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-28 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDS tSDH SCKE A10/AP nGCS x tSCSD nWE tSAD tSCD tSWD '1' Trcd tSBED Tcl Tcl Tcl Figure 2.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-29 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD SCKE A10/AP nGCS x tSCSD nW E tSAD tSCD tSW D tSAD tSCSD tSRD '1' '1' 'HZ&.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-30 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDD tSDD SCKE A10/AP nGCSx tSCSD nW E tSAD tSCD tSW D '1' tSAD tSAD Trc d tSCSD tSRD tSCSD tSAD tSAD tSBED tSW D Figure 27-28.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-31 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDD tSDD SCKE A10/A P nGCSx tSCS D nWE tSAD tSCD tSWD '1' Trcd tSBED Figure 27-29.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-32 XSC L K tXRS tXRS tCAD L tCADH tXAD Xn XD RE Q XnXDACK Read Wr it e Min . 3 SC LK Figure 27-30. Extern al DMA Timing Diagram ( Handshake, Sing le tr.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-33 IISSCLK tLRCK IISLRCK (out) tSDO IISLRCK (out) tSDIH tSDIS IISSDI (in) Figure 27-32. IIS Int erface Timin g Diagram tST OPH tSTAR TS tSDA S tSDAH tBUF tS CLHI GH tS CLLOW fSCL IICSC L IICSD A Figure 27-33.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-34 SDCLK tSDCD SDCM D (out) tSDCH tSDCS tSDDD SDCM D (in) tSDDH tSDDS SDDATA[ 3:0] (in) SDDATA[ 3:0] (out) Figure 27-34. SD/M M C Interf ace Timing Diag ram SPICLK tSPIM OD tSPISIH tSPIS IS tSPISOD tSPIM IH tSPIM IS SPIM OSI (MO ) SPIM OSI (SI) SPIM ISO (SO) SPIM ISO (M I) Figure 27-35.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-35 TA CL S TWR PH 0 TWR PH 1 COMMAND TW RPH0 T W RPH 1 ADDR ESS HCLK ALE nFW E DAT A[7:0] DAT A[7:0] HCLK CLE nFW E tCL ED tCL ED tWED tW ED tWDS tW DH tALED tW ED tWDS tALED tWED tWDH TACLS Figure 27-36.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-36 Table 27- 7 Clock Timin g Constant s (V DDi, V DDalive, V DDiarm = 1.2 V ± 0.1 V, T A = -40 to 85 ° C, V DDMOP = 3.3V ± 0.3V) Parame ter Symbol Min T yp M ax Unit Crystal clock input f requency f XT AL 12 – 20 MHz Crystal clock input c y c le time t XTA LC Y C 50 – 83.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-37 Table 27- 8 ROM /SRA M Bus T iming Const ants (V DDi, V DDalive, V DDiarm = 1.2 V ± 0.1 V, T A = -40 to 85 ° C, V DDMOP = 3.3V ± 0.3V / 3.0V ± 0.3V / 2.5V ± 0.2V / 1.8V ± 0.1V) Parameter Symbo l Mi n (V DDMOP = 3.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-38 Table 27- 10 External Bus Request Timing Constant s (V DD = 1.2 V ± 0.1 V, T A = -40 to 85 ° C, V EXT = 3.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-39 Table 27-12 TFT LCD Controller M odule Signal Timing Constants (V DD = 1.2 V ± 0.05 V, T A = -40 to 85 ° C, V EXT = 3.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-40 Table 27-14 IIC BUS Controller Module Signal Timing (V DD = 1.2 V ± 0.05 V, T A = -40 to 85 ° C, V EXT = 3.3V ± 0.3V) Parame ter Sy mbol Min Typ. M ax Unit SCL Clock Frequency f SCL – – std. 100 fast 400 KHz SCL High Level Pulse W idth t SCLHIGH std.
S3C2440A RISC MICROPROCESSOR ELECTRICAL DA TA 27-41 Table 27- 16 SPI Interface T ransmit/Receive T iming Co nstants (V DD = 1.2 V ± 0.1 V, T A = -40 to 85 ° C, V EXT = 3.
ELECTRICAL DA TA S3C2440A RISC MICROPROCESSOR 27-42 Table 27- 18 USB Full Speed Outp ut Buff er Electrical Characteristics (V DD = 1.2 V ± 0.05 V, T A = -40 to 85 ° C, V EXT = 3.3V ± 0.3V) Parame ter Sy mbol Condition Min Max Unit Driver Characterist ics Trans ition Tim e Rise Tim e Fall T im e TR TF CL = 50pF CL = 50pF 4.
Un punto importante, dopo l’acquisto del dispositivo (o anche prima di acquisto) è quello di leggere il manuale. Dobbiamo farlo per diversi motivi semplici:
Se non hai ancora comprato il Samsung S3C2440A è un buon momento per familiarizzare con i dati di base del prodotto. Prime consultare le pagine iniziali del manuale d’uso, che si trova al di sopra. Dovresti trovare lì i dati tecnici più importanti del Samsung S3C2440A - in questo modo è possibile verificare se l’apparecchio soddisfa le tue esigenze. Esplorando le pagine segenti del manuali d’uso Samsung S3C2440A imparerai tutte le caratteristiche del prodotto e le informazioni sul suo funzionamento. Le informazioni sul Samsung S3C2440A ti aiuteranno sicuramente a prendere una decisione relativa all’acquisto.
In una situazione in cui hai già il Samsung S3C2440A, ma non hai ancora letto il manuale d’uso, dovresti farlo per le ragioni sopra descritte. Saprai quindi se hai correttamente usato le funzioni disponibili, e se hai commesso errori che possono ridurre la durata di vita del Samsung S3C2440A.
Tuttavia, uno dei ruoli più importanti per l’utente svolti dal manuale d’uso è quello di aiutare a risolvere i problemi con il Samsung S3C2440A. Quasi sempre, ci troverai Troubleshooting, cioè i guasti più frequenti e malfunzionamenti del dispositivo Samsung S3C2440A insieme con le istruzioni su come risolverli. Anche se non si riesci a risolvere il problema, il manuale d’uso ti mostrerà il percorso di ulteriori procedimenti – il contatto con il centro servizio clienti o il servizio più vicino.
