Manuale d’uso / di manutenzione del prodotto Low-Cost Multifunction I/O Board for ISA Lab-PC+ del fabbricante National Instruments
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© Copyright 1992, 1996 National Instruments Corporation. All Rights Reserved. Lab-PC+ User Manual Low-Cost Multifunction I/O Board for ISA June 1996 Edition Part Number 320502B -01.
National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin, TX 78730-5039 (512) 794-0100 Technical support fax: (512) 794-5678 Branch Offices: Australia 03 9 879 9422, Austria 0662 4.
Warranty The Lab -PC+ board is warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period.
WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans.
© National Instruments Corporation v Lab-PC+ User Manual Contents About This Manual ........................................................................................................... xi Organization of the Lab-PC+ User Manual ...............
Contents Lab-PC+ User Manual vi © National Instruments Corporation Chapter 3 Signal Connections ............................................................................................................ 3-1 I/O Connector Pin Description ...........
Contents © National Instruments Corporation vii Lab-PC+ User Manual Chapter 5 Calibration ............................................................................................................................. 5-1 Calibration Equipment Requirements .
Contents Lab-PC+ User Manual viii © National Instruments Corporation Figures Figure 1-1. The Relationship between the Programming Environment, NI -DAQ, and Your Hardware ............................................................................ 1-3 Figure 2-1.
Contents © National Instruments Corporation ix Lab-PC+ User Manual Tables Table 2-1. PC Bus Interface Factory Settings ..................................................................... 2-3 Table 2-2. Switch Settings with Corresponding Base I/O Address and Base I/O Address Space .
© National Instruments Corporation xi Lab-PC+ User Manual About This Manual This manual describes the electrical and mechanical aspects of the Lab-PC+ and contains information concerning its operation and programming. The Lab-PC+ is a low-cost multifunction analog, digital, and timing I/O board for PC compatible computers.
About This Manual Lab-PC+ User Manual xii © National Instruments Corporation • The Glossary contains an alphabetical list and description of terms used in this manual, including abbreviations, acronyms, metric prefixes, mnemonics, and symbols.
About this Manual © National Instruments Corporation xiii Lab-PC+ User Manual National Instruments Documentation The Lab-PC+ User Manual is one piece of the documentation set for your DAQ system. You could have any of several types of manuals depending on the hardware and software in your system.
© National Instruments Corporation 1-1 Lab-PC+ User Manual Chapter 1 Introduction This chapter describes the Lab -PC+; lists what you need to get started; describes the optional software and optional equipment; and explains how to unpack the Lab-PC+.
Introduction Chapter 1 Lab-PC+ User Manual 1-2 © National Instruments Corporation Software Programming Choices There are several options to choose from when programming your National Instruments DAQ and SCXI hardware. You can use LabVIEW, LabWindows/CVI, NI-DAQ, or register-level programming.
Chapter 1 Introduction © National Instruments Corporation 1-3 Lab-PC+ User Manual NI -DAQ also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA controllers.
Introduction Chapter 1 Lab-PC+ User Manual 1-4 © National Instruments Corporation Optional Equipment National Instruments offers a variety of products to use with your Lab-PC+ board, including cables.
© National Instruments Corporation 2-1 Lab-PC+ User Manual Chapter 2 Configuration and Installation This chapter describes the Lab -PC+ jumper configuration and installation of the Lab-PC+ board in your computer. Board Configuration The Lab-PC+ contains six jumpers and one DIP switch to configure the PC bus interface and analog I/O settings.
Configuration and Installation Chapter 2 Lab-PC+ User Manual 2-2 © National Instruments Corporation 1 2 3 4 7 8 9 5 6 13 12 11 10 1 Assembly Number 5 W2 8 Serial Number 11 W6 2 Spare Fuse 6 W3 9 J1 12 W5 3 U1 7 W4 10 Fuse 13 Product Name 4W 1 Figure 2-1.
Chapter 2 Configuration and Installation © National Instruments Corporation 2-3 Lab-PC+ User Manual Table 2-1. PC Bus Interface Factory Settings Lab -PC+ Board Default Settings Hardware Implementatio.
Configuration and Installation Chapter 2 Lab-PC+ User Manual 2-4 © National Instruments Corporation A9 A8 A7 A6 A5 1 2 3 4 5 O N O F F U1 This side down for 0 — This side down for 1 — A. Switches Set to Base I/O Address of Hex 000 A9 A8 A7 A6 A5 1 2 3 4 5 O N O F F U1 This side down for 0 — This side down for 1 — B.
Chapter 2 Configuration and Installation © National Instruments Corporation 2-5 Lab-PC+ User Manual Table 2-2. Switch Settings with Corresponding Base I/O Address and Base I/O Address Space Switch Se.
Configuration and Installation Chapter 2 Lab-PC+ User Manual 2-6 © National Instruments Corporation DMA Channel Selection The Lab-PC+ uses the DMA channel selected by jumpers on W6 (see Figure 2 -1). The Lab-PC+ is set at the factory to use DMA Channel 3.
Chapter 2 Configuration and Installation © National Instruments Corporation 2-7 Lab-PC+ User Manual • • • • • • • • • • • • • • • • DACK* DRQ W6 12 3 Figure 2-4.
Configuration and Installation Chapter 2 Lab-PC+ User Manual 2-8 © National Instruments Corporation If you do not want to use interrupts, place the jumper on W5 in the position shown in Figure 2-6. This setting disables the Lab-PC+ from asserting an interrupt line on the PC I/O channel.
Chapter 2 Configuration and Installation © National Instruments Corporation 2-9 Lab-PC+ User Manual Table 2-4. Analog I/O Jumper Settings Parameter Configuration Jumper Settings Output CH0 Polarity B.
Configuration and Installation Chapter 2 Lab-PC+ User Manual 2-10 © National Instruments Corporation Unipolar Output Selection You can select the unipolar (0 V to 10 V) output configuration for eithe.
Chapter 2 Configuration and Installation © National Instruments Corporation 2-11 Lab-PC+ User Manual Table 2-5. Input Configurations Available for the Lab -PC+ Configuration Description DIFF Differen.
Configuration and Installation Chapter 2 Lab-PC+ User Manual 2-12 © National Instruments Corporation This configuration is shown in Figure 2-9. W4 • A B C RSE NRSE/DIFF Figure 2-9. DIFF Input Configuration Considerations in using the DIFF configuration are discussed in Chapter 3, Signal Connections .
Chapter 2 Configuration and Installation © National Instruments Corporation 2-13 Lab-PC+ User Manual NRSE Input (Eight Channels) NRSE input means that all input signals are referenced to the same common mode voltage, which is allowed to float with respect to the analog ground of the Lab-PC+ board.
Configuration and Installation Chapter 2 Lab-PC+ User Manual 2-14 © National Instruments Corporation • • • A B C W3 B U Figure 2-12. Bipolar Input Jumper Configuration (Factory Setting) Unipola.
Chapter 2 Configuration and Installation © National Instruments Corporation 2-15 Lab-PC+ User Manual Hardware Installation The Lab-PC+ can be installed in any available 8-bit or 16-bit expansion slot in your computer.
© National Instruments Corporation 3-1 Lab-PC+ User Manual Chapter 3 Signal Connections This chapter describes how to make input and output signal connections to your Lab-PC+ board via the board I/O connector. I/O Connector Pin Description Figure 3-1 shows the pin assignments for the Lab -PC+ I/O connector.
Signal Connections Chapter 3 Lab-PC+ User Manual 3-2 © National Instruments Corporation 12 34 56 78 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 .
Chapter 3 Signal Connections © National Instruments Corporation 3-3 Lab-PC+ User Manual Pin Signal Name Description 1-8 ACH0 through ACH7 Analog input Channels 0 through 7 (single-ended). 9 AISENSE/AIGND Analog input ground in RSE mode, AISENSE in NRSE mode.
Signal Connections Chapter 3 Lab-PC+ User Manual 3-4 © National Instruments Corporation The connector pins can be grouped into analog input signal pins, analog output signal pins, digital I/O signal pins, and timing I/O signal pins. Signal connection guidelines for each of these groups are included later in this chapter.
Chapter 3 Signal Connections © National Instruments Corporation 3-5 Lab-PC+ User Manual - + Instrumentation Amplifier + - Measured V oltage V m = [V in + - V in -] * GAIN V in - V m V in + Figure 3-2.
Signal Connections Chapter 3 Lab-PC+ User Manual 3-6 © National Instruments Corporation the measured input signal varies or appears to float. An instrument or device that provides an isolated output falls into the floating signal source category.
Chapter 3 Signal Connections © National Instruments Corporation 3-7 Lab-PC+ User Manual When the Lab-PC+ is configured for DIFF input, each signal uses two of the multiplexer inputs – one for the signal and one for its reference signal. Therefore, only four analog input channels are available when using the DIFF configuration.
Signal Connections Chapter 3 Lab-PC+ User Manual 3-8 © National Instruments Corporation + - + Grounded Signal Source V m Measured V oltage - V s - + I/O Connector Lab-PC+ Board in DIFF Configuration .
Chapter 3 Signal Connections © National Instruments Corporation 3-9 Lab-PC+ User Manual + - + Floating Signal Source V m Measured V oltage - V s - + I/O Connector Lab-PC+ Board in DIFF Configuration .
Signal Connections Chapter 3 Lab-PC+ User Manual 3-10 © National Instruments Corporation Single-Ended Connection Considerations Single-ended connections are those in which all Lab-PC+ analog input signals are referenced to one common ground.
Chapter 3 Signal Connections © National Instruments Corporation 3-11 Lab-PC+ User Manual V s + + + - - - V m Measured V oltage Floating Signal Source ACH 0 AISENSE/AIGND AGND I/O Connector 1 2 3 8 9 Lab-PC+ Board in RSE Configuration 11 ACH 1 ACH 2 ACH 7 Figure 3-5.
Signal Connections Chapter 3 Lab-PC+ User Manual 3-12 © National Instruments Corporation ACH 0 V m Measured V oltage Common Mode Noise and so on AGND AISENSE/AIGND V s V cm - - + + - + - + I/O Connector Lab-PC+ Board in NRSE Input Configuration 1 2 3 8 9 11 Ground- Referenced Signal Source ACH 1 ACH 2 ACH 7 Figure 3-6.
Chapter 3 Signal Connections © National Instruments Corporation 3-13 Lab-PC+ User Manual Pin 11, AGND, is the ground reference point for both analog output channels as well as analog input.
Signal Connections Chapter 3 Lab-PC+ User Manual 3-14 © National Instruments Corporation are connected to the digital lines PC<0..7> for digital I/O Port C. Pin 13, DGND, is the digital ground pin for all three digital I/O ports. The following specifications and ratings apply to the digital I/O lines.
Chapter 3 Signal Connections © National Instruments Corporation 3-15 Lab-PC+ User Manual 14 P A0 22 PB0 30 PC0 13 DGND Lab-PC+ Board Switch I/O Connector +5 V +5 V LED TTL Signal Port B PB<7..0> Port A P A<7..0> Port C PC<7..0> Figure 3-8.
Signal Connections Chapter 3 Lab-PC+ User Manual 3-16 © National Instruments Corporation Table 3-2. Port C Signal Assignments Programmable Mode Group A Group B PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Mode 0 .
Chapter 3 Signal Connections © National Instruments Corporation 3-17 Lab-PC+ User Manual Name Type Description (continued) OBF* Output Output buffer full–A low signal on this handshaking line indicates that data has been written from the specified port.
Signal Connections Chapter 3 Lab-PC+ User Manual 3-18 © National Instruments Corporation Mode 1 Input Timing The timing specifications for an input transfer in Mode 1 are as follows: DA T A RD * INTR.
Chapter 3 Signal Connections © National Instruments Corporation 3-19 Lab-PC+ User Manual Mode 1 Output Timing The timing specifications for an output transfer in Mode 1 are as follows: WR* OBF* INTR .
Signal Connections Chapter 3 Lab-PC+ User Manual 3-20 © National Instruments Corporation Mode 2 Bidirectional Timing The timing specifications for bidirectional transfers in Mode 2 are as follows: T1.
Chapter 3 Signal Connections © National Instruments Corporation 3-21 Lab-PC+ User Manual Timing Connections Pins 38 through 48 of the I/O connector are connections for timing I/O signals. The timing I/O of the Lab-PC+ is designed around the 8253 Counter/Timer integrated circuit.
Signal Connections Chapter 3 Lab-PC+ User Manual 3-22 © National Instruments Corporation and 3-11 illustrate two possible posttrigger data acquisition timing cases. In Figure 3-10, the rising edge on EXTTRIG is sensed when the EXTCONV* input is high.
Chapter 3 Signal Connections © National Instruments Corporation 3-23 Lab-PC+ User Manual If PRETRIG is set, EXTTRIG serves as a pretrigger signal. In pretrigger mode, A/D conversions are enabled via software before a rising edge is sensed on the EXTTRIG input.
Signal Connections Chapter 3 Lab-PC+ User Manual 3-24 © National Instruments Corporation t ext Minimum 50 nsec EXTUPDA TE* DAC OUTPUT UPDA TE CNTINT DACWR T t ext Figure 3-13.
Chapter 3 Signal Connections © National Instruments Corporation 3-25 Lab-PC+ User Manual measurement. For these applications, CLK and GATE signals are sent to the counters, and the counters are programmed for various operations. The single exception is counter B0, which has an internal 2 MHz clock.
Signal Connections Chapter 3 Lab-PC+ User Manual 3-26 © National Instruments Corporation counting after receiving a low-to-high edge. The time lapse since receiving the edge equals the counter value difference (loaded value minus read value) multiplied by the CLK period.
Chapter 3 Signal Connections © National Instruments Corporation 3-27 Lab-PC+ User Manual The following specifications and ratings apply to the 8253 I/O signals: Absolute maximum voltage input rating: -0.5 to 7.0 V with respect to DGND 8253 digital input specifications (referenced to DGND): V IH input logic high voltage 2.
Signal Connections Chapter 3 Lab-PC+ User Manual 3-28 © National Instruments Corporation The GATE and OUT signals in Figure 3-17 are referenced to the rising edge of the CLK signal. Cabling National Instruments currently offers a cable termination accessory, the CB-50, for use with the Lab -PC+ board.
© National Instruments Corporation 4-1 Lab-PC+ User Manual Chapter 4 Theory of Operation This chapter contains a functional overview of the Lab -PC+ and explains the operation of each functional unit making up the Lab -PC+. This chapter also explains the basic operation of the Lab -PC+ circuitry.
Theory of Operation Chapter 4 Lab-PC+ User Manual 4-2 © National Instruments Corporation The following are the major components making up the Lab-PC+ board: • PC I/O channel interface circuitry •.
Chapter 4 Theory of Operation © National Instruments Corporation 4-3 Lab-PC+ User Manual Address Bus Address Latches Address Decoder T iming Interface Data Buffers DMA Control Interrupt Control Contr.
Theory of Operation Chapter 4 Lab-PC+ User Manual 4-4 © National Instruments Corporation • When a digital I/O port is ready to transfer data • When a rising edge signal is detected on Counter A2 output or on the EXTUPDATE line Each one of these interrupts is individually enabled and cleared.
Chapter 4 Theory of Operation © National Instruments Corporation 4-5 Lab-PC+ User Manual Analog Input Circuitry The analog input circuitry consists of two CMOS analog input multiplexers, a software- programmable gain amplifier, a 12-bit ADC, and a 12 -bit FIFO memory that is sign-extended to 16 bits.
Theory of Operation Chapter 4 Lab-PC+ User Manual 4-6 © National Instruments Corporation (scanned) data acquisition in two modes–continuous and interval. The Lab-PC+ uses a counter to switch between analog input channels automatically during scanned data acquisition.
Chapter 4 Theory of Operation © National Instruments Corporation 4-7 Lab-PC+ User Manual You must initialize two additional counters to operate in interval acquisition mode.
Theory of Operation Chapter 4 Lab-PC+ User Manual 4-8 © National Instruments Corporation Table 4-2. Lab-PC+ Maximum Recommended Data Acquisition Rates Acquisition Mode Gain Setting Rate Single Channel 1 2, 5, 10, 20, 50, 100 83.3 ksamples/s 71.4 ksamples/s* Multiple Channel 1 2, 5, 10, 20, 50 100 83.
Chapter 4 Theory of Operation © National Instruments Corporation 4-9 Lab-PC+ User Manual Analog Output Circuitry The Lab-PC+ provides two channels of 12-bit D/A output. Each analog output channel can provide unipolar or bipolar output. Figure 4-4 shows a block diagram of the analog output circuitry.
Theory of Operation Chapter 4 Lab-PC+ User Manual 4-10 © National Instruments Corporation Each DAC channel can be jumper-programmed for either a unipolar voltage output or a bipolar voltage output range. A unipolar output gives an output voltage range of 0.
Chapter 4 Theory of Operation © National Instruments Corporation 4-11 Lab-PC+ User Manual All three ports on the 8255A are TTL-compatible. When enabled, the digital output ports are capable of sinking 2.4 mA of current and sourcing 2.6 mA of current on each digital I/O line.
Theory of Operation Chapter 4 Lab-PC+ User Manual 4-12 © National Instruments Corporation A/D Conversion Logic N/C 1 MHz Source OUTB0 CLKA0 GA TEB0 OUTB0 CCLKB1 GA TEB1 OUTB2 GA TEB2 CLKB2 D/A Conver.
Chapter 4 Theory of Operation © National Instruments Corporation 4-13 Lab-PC+ User Manual Each 8253 contains three independent 16 -bit counter/timers and one 8-bit Mode Register. As shown in Figure 4-6, Counter Group A is reserved for data acquisition timing, and Counter Group B is free for general use.
Theory of Operation Chapter 4 Lab-PC+ User Manual 4-14 © National Instruments Corporation OUTB1 OUT A0 Interval Counter Sample Interval Scan Interval CONVER T GA TEA0 Sample Interval Figure 4-8. Single-Channel Interval Timing The 16 -bit counters in the 8253 can be diagrammed as shown in Figure 4-9.
© National Instruments Corporation 5-1 Lab-PC+ User Manual Chapter 5 Calibration This chapter discusses the calibration procedures for the Lab-PC+ analog input and analog output circuitry.
Calibration Chapter 5 Lab-PC+ User Manual 5-2 © National Instruments Corporation Calibration Trimpots The Lab-PC+ has six trimpots for calibration. The location of these trimpots on the Lab -PC+ board is shown in the partial diagram of the board in Figure 5-1.
Chapter 5 Calibration © National Instruments Corporation 5-3 Lab-PC+ User Manual Analog Input Calibration To null out error sources that compromise the quality of measurements, you must calibrate the.
Calibration Chapter 5 Lab-PC+ User Manual 5-4 © National Instruments Corporation The voltages corresponding to V -fs , which is the most negative voltage that the ADC can read, V +fs - 1, which is the most positive voltage the ADC can read, and 1 LSB, which is the voltage corresponding to one count of the ADC, depend on the input range selected.
Chapter 5 Calibration © National Instruments Corporation 5-5 Lab-PC+ User Manual later for software offset correction of the data at gains other than 1, thus eliminating the need to perform the input offset recalibration when a different gain is used.
Calibration Chapter 5 Lab-PC+ User Manual 5-6 © National Instruments Corporation 3. Gain Calibration Adjust the analog input gain by applying an input voltage across ACH0 and AISENSE/AIGND. This input voltage is +9.99634 V or V +fs - 1.5 LSB. a. Connect the calibration voltage (+9.
Chapter 5 Calibration © National Instruments Corporation 5-7 Lab-PC+ User Manual 1. Adjust the Analog Output Offset Adjust the analog output offset by measuring the output voltage generated with the DAC set at negative full-scale (0). This output voltage should be V -fs ± 0.
Calibration Chapter 5 Lab-PC+ User Manual 5-8 © National Instruments Corporation Unipolar Output Calibration Procedure If your analog output channel is configured for unipolar output, which has an output range of 0 to +10 V, then offset calibration is not needed.
© National Instruments Corporation A-1 Lab-PC+ User Manual Appendix A Specifications This appendix lists the specifications of the Lab -PC+. These specifications are typical at 25 ° C unless otherwise stated. The operating temperature range is 0 ° to 70 ° C.
Specifications Appendix A Lab-PC+ User Manual A-2 © National Instruments Corporation Amplifier Characteristics Input impedance ............................................ 0.1 G Ω in parallel with 45 pF Input bias current ..........................
Appendix A Specifications © National Instruments Corporation A-3 Lab-PC+ User Manual Explanation of Analog Input Specifications Relative accuracy is a measure of the linearity of an ADC. However, relative accuracy is a tighter specification than a nonlinearity specification.
Specifications Appendix A Lab-PC+ User Manual A-4 © National Instruments Corporation Analog Output Output Characteristics Number of channels ...................................... 2 Resolution ..................................................... 12 bits, 1 in 4,096 Type of DAC .
Appendix A Specifications © National Instruments Corporation A-5 Lab-PC+ User Manual Differential nonlinearity (DNL) in a D/A system is a measure of deviation of code width from 1 LSB. In this case, code width is the difference between the analog values produced by consecutive digital codes.
Specifications Appendix A Lab-PC+ User Manual A-6 © National Instruments Corporation Digital logic levels ........................................ Level Min Max Input low voltage Input high voltage -0.3 V 2.2 V 0.8 V 5.3 V Output low voltage (I out = 4 mA) Output high voltage (I out = -1 mA) - 3.
© National Instruments Corporation B-1 Lab-PC+ User Manual Appendix B OKI 82C53 Data Sheet * This appendix contains the manufacturer data sheet for the OKI 82C53 System Timing Controller integrated circuit (OKI Semiconductor). This circuit is used on the Lab-PC+.
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© National Instruments Corporation C-1 Lab-PC+ User Manual Appendix C OKI 82C55A Data Sheet * This appendix contains the manufacturer data sheet for the OKI 82C55A Programmable Peripheral Interface integrated circuit (OKI Semiconductor). This circuit is used on the Lab -PC+.
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© National Instruments Corporation D- 1 Lab-PC+ User Manual Appendix D Register Map and Descriptions This appendix describes in detail the address and function of each of the Lab-PC+ registers.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 2 © National Instruments Corporation Table D-1. Lab -PC+ Register Map Register Name Offset Address (Hex) Type Size Configuration and St.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 3 Lab-PC+ User Manual Register Sizes The Lab-PC+ registers are 8-bit registers. To transfer 16-bit data, two consecutive I/O readings or writings are needed. For example, to read the 16-bit A/D conversion result, two consecutive 8-bit readings of FIFO are needed.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 4 © National Instruments Corporation Configuration and Status Register Group The five registers making up the Configuration and Status Register Group allow general control and monitoring of the Lab-PC+ A/D and D/A circuitry.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 5 Lab-PC+ User Manual Command Register 1 Command Register 1 indicates the input channel to be read, the gain for the analog input circuitry, and the range of the input signal (unipolar or bipolar).
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 6 © National Instruments Corporation Bit Name Description (continued) 3 TWOSCMP This bit selects the format of the coding of the output of the ADC. If this bit is set, the 12-bit data from the ADC is sign-extended to 16 bits.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 7 Lab-PC+ User Manual Status Register The Status Register indicates the status of the current A/D conversion. The bits in this register determine if a conversion is being performed or if data is available, whether any errors have been found, and the interrupt status.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 8 © National Instruments Corporation Bit Name Description (continued) 1 OVERRUN This bit indicates if an overrun error has occurred. If this bit is cleared, no error occurred. This bit is set if a convert command is issued to the ADC while the last conversion is still in progress.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 9 Lab-PC+ User Manual Command Register 2 Command Register 2 contains eight bits that control Lab-PC+ analog input trigger modes and analog output modes.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 10 © National Instruments Corporation Bit Name Description (continued) 2 SWTRIG This bit enables and disables a data acquisition operation that is controlled by Counter A0 and Counter A1.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 11 Lab-PC+ User Manual Command Register 3 The Command Register 3 contains six bits that enable and disable the interrupts and DMA operation.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 12 © National Instruments Corporation Bit Name Description (continued) 1 DIOINTEN This bit enables or disables generation of an interrupt when either Port A or Port B is ready to transfer data, and an interrupt request is set via PC3 or PC0 of 8255A.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 13 Lab-PC+ User Manual Command Register 4 This register allows multiplexing of certain A/D conversion logic signals.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 14 © National Instruments Corporation Bit Name Description (continued) 2 ECKDRV This bit controls the direction of the EXTCONV* line on the I/O Connector. If this bit is clear, EXTCONV* is driven from the I/O Connector into the conversion circuitry.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 15 Lab-PC+ User Manual Analog Input Register Group The four registers making up the Analog Input Register Group control the analog input circuitry and can be used to read the FIFO.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 16 © National Instruments Corporation A/D FIFO Register The 12 -bit A/D conversion results are sign-extended to 16-bit data in either two's complement or straight binary format and are stored into a 512-word deep A/D FIFO buffer.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 17 Lab-PC+ User Manual Bit Name Description (continued) Low Byte 7-0 D<7..0> These bits contain the low byte of the straight binary result of a 12-bit A/D conversion.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 18 © National Instruments Corporation A/D Clear Register The ADC can be reset by writing to this register. This operation clears the FIFO and loads the last conversion value into the FIFO.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 19 Lab-PC+ User Manual Start Convert Register Writing to the Start Convert Register location initiates an A/D conversion.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 20 © National Instruments Corporation DMATC Interrupt Clear Register Writing to the DMA Terminal Count (DMATC) Clear Register clears the interrupt request asserted when a DMA terminal count pulse is detected.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 21 Lab-PC+ User Manual Analog Output Register Group The four registers making up the Analog Output Register Group are used for loading the two 12-bit DACs in the two analog output channels.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 22 © National Instruments Corporation DAC0 Low-Byte (DAC0L), DAC0 High-Byte (DAC0H), DAC1 Low-Byte (DAC1L), and DAC1 High-Byte (DAC1H) Registers Writing to DAC0L and then to DAC0H loads the analog output Channel 0.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 23 Lab-PC+ User Manual 8253 Counter/Timer Register Groups A and B The nine registers making up the two Counter/Timer Register Groups access the two onboard 8253 Counter/Timers.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 24 © National Instruments Corporation Counter A0 Data Register The Counter A0 Data Register is used for loading and reading back contents of 8253(A) Counter 0.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 25 Lab-PC+ User Manual Counter A1 Data Register The Counter A1 Data Register is used for loading and reading back contents of 8253(A) Counter 1.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 26 © National Instruments Corporation Counter A2 Data Register The Counter A2 Data Register is used for loading and reading back contents of 8253(A)Counter A2.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 27 Lab-PC+ User Manual Counter A Mode Register The Counter A Mode Register determines the operation mode for each of the three counters on the 8253(A) chip.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 28 © National Instruments Corporation Timer Interrupt Clear Register Writing to the Timer Interrupt Clear Register clears the interrupt request asserted when a low pulse is detected on the Counter A2 output or on EXTUPDATE* line.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 29 Lab-PC+ User Manual Counter B0 Data Register The Counter B0 Data Register is used for loading and reading back the contents of 8253(B) Counter 0.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 30 © National Instruments Corporation Counter B1 Data Register The Counter B1 Data Register is used for loading and reading back the contents of 8253(B) Counter 1.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 31 Lab-PC+ User Manual Counter B2 Data Register The Counter B2 Data Register is used for loading and reading back the contents of 8253(B) Counter 2.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 32 © National Instruments Corporation Counter B Mode Register The Counter B Mode Register determines the operation mode for each of the three counters on the 8253(B) chip.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 33 Lab-PC+ User Manual 8255A Digital I/O Register Group Digital I/O on the Lab -PC+ uses an 8255A integrated circuit. The 8255A is a general-purpose peripheral interface containing 24 programmable I/O pins.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 34 © National Instruments Corporation Port A Register Reading the Port A Register returns the logic state of the eight digital I/O lines constituting Port A, that is, PA<0.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 35 Lab-PC+ User Manual Port B Register Reading the Port B Register returns the logic state of the eight digital I/O lines constituting Port B, that is, PB<0.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 36 © National Instruments Corporation Port C Register Port C is special in the sense that it can be used as an 8-bit I/O port like Port A and Port B if neither Port A nor Port B is used in handshaking (latched) mode.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 37 Lab-PC+ User Manual Digital Control Register The Digital Control Register can be used to configure Port A, Port B, and Port C as inputs or outputs as well as selecting simple mode (basic I/O) or handshaking mode (strobed I/O) for transfers.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 38 © National Instruments Corporation Interval Counter Register Group The 8 -bit Interval Counter is used only in the single-channel in.
Appendix D Register Map and Descriptions © National Instruments Corporation D- 39 Lab-PC+ User Manual Interval Counter Data Register The Interval Counter Data Register is loaded with the desired number of samples of a single channel that will be acquired between intervals.
Register Map and Descriptions Appendix D Lab-PC+ User Manual D- 40 © National Instruments Corporation Interval Counter Strobe Register Writing to Interval Counter Strobe Register strobes the contents of the Interval Counter Data Register into the Interval Counter.
© National Instruments Corporation E-1 Lab-PC+ User Manual Appendix E Register-Level Programming This appendix contains important information about programming the Lab-PC+. Programming the Lab-PC+ involves writing to and reading from the various registers on the board.
Register-Level Programming Appendix E Lab-PC+ User Manual E-2 © National Instruments Corporation 8. Write 00 (hex) to the DMATC Interrupt Clear Register. 9. Write 00 (hex) to the Timer Interrupt Clear Register. 10. Write 00 (hex) to the A/D Clear Register.
Appendix E Register-Level Programming © National Instruments Corporation E-3 Lab-PC+ User Manual Analog Input Circuitry Programming Sequence Programming the analog input circuitry for a single A/D conversion involves selecting the analog input channel and gain, initiating an A/D conversion, and reading the A/D conversion result.
Register-Level Programming Appendix E Lab-PC+ User Manual E-4 © National Instruments Corporation The DAVAIL bit indicates whether one or more A/D conversion results are stored in the A/D FIFO. If the DAVAIL bit is cleared, the A/D FIFO is empty and reading the A/D FIFO Register returns meaningless data.
Appendix E Register-Level Programming © National Instruments Corporation E-5 Lab-PC+ User Manual Clearing the Analog Input Circuitry The analog input circuitry can be cleared by writing to the A/D Clear Register, which leaves the analog input circuitry in the following state: • Analog input error flags OVERFLOW and OVERRUN are cleared.
Register-Level Programming Appendix E Lab-PC+ User Manual E-6 © National Instruments Corporation Alternatively, a programmable timebase for Counter A0 is available through the use of Counter B0. If the TBSEL bit in Command Register 1 is set, then the timebase for Counter A0 is Counter B0.
Appendix E Register-Level Programming © National Instruments Corporation E-7 Lab-PC+ User Manual 3. Program Counters A0 and A1. This step involves programming Counter A0 (the sample interval counter) in rate generator mode (Mode 2) and programming Counter A1 to interrupt on terminal count mode (Mode 0).
Register-Level Programming Appendix E Lab-PC+ User Manual E-8 © National Instruments Corporation Once the data acquisition operation is started, the operation must be serviced by reading the A/D FIFO Register every time an A/D conversion result becomes available.
Appendix E Register-Level Programming © National Instruments Corporation E-9 Lab-PC+ User Manual 1. Select analog input channel, gain, and timebase for Counter A0. The analog input channel and gain are selected by writing to the A/D Configuration Register.
Register-Level Programming Appendix E Lab-PC+ User Manual E-10 © National Instruments Corporation 4. Program Counter A1 to force OUT1 low. If OUT1 is high, Counter A0 is disabled. Write 70 (hex) to the Counter A Mode Register (select Counter A1, Mode 0) to force OUT1 low.
Appendix E Register-Level Programming © National Instruments Corporation E-11 Lab-PC+ User Manual External Timing Considerations for Multiple A/D Conversions Two external timing signals, EXTTRIG and EXTCONV*, can be used for multiple A/D conversions.
Register-Level Programming Appendix E Lab-PC+ User Manual E-12 © National Instruments Corporation Using the EXTCONV* Signal to Initiate A/D Conversions As mentioned earlier, A/D conversions can be initiated by a falling edge on either OUTA0 or EXTCONV*.
Appendix E Register-Level Programming © National Instruments Corporation E-13 Lab-PC+ User Manual 3. Program Counter A0. Since a high-to-low transition on the Counter A0 output initiates an A/D conversion, Counter A0 output must be programmed to a high state.
Register-Level Programming Appendix E Lab-PC+ User Manual E-14 © National Instruments Corporation Two error conditions may occur during a data acquisition operation: an overflow error or an overrun error.
Appendix E Register-Level Programming © National Instruments Corporation E-15 Lab-PC+ User Manual 2. Program Counter A0. Since a high-to-low transition on the Counter A0 output initiates an A/D conversion, Counter A0 output must be programmed to a high state.
Register-Level Programming Appendix E Lab-PC+ User Manual E-16 © National Instruments Corporation 5. Start and service the data acquisition operation.
Appendix E Register-Level Programming © National Instruments Corporation E-17 Lab-PC+ User Manual Pretrigger Mode Pretriggering mode requires that the A/D conversions be shut off at a programmed time by the hardware after the trigger on EXTTRIG. Therefore, pretriggered data acquisition is not possible in freerun acquisition mode.
Register-Level Programming Appendix E Lab-PC+ User Manual E-18 © National Instruments Corporation acquisition operation is fully configured. Use the following sequence to configure the Lab-PC+ for interval scanning: 1.
Appendix E Register-Level Programming © National Instruments Corporation E-19 Lab-PC+ User Manual another N samples and the cycle repeats. The operation stops when the sample counter (Counter A1) decrements to 0. Use the following sequence to configure the Lab-PC+ for single-channel interval acquisition mode.
Register-Level Programming Appendix E Lab-PC+ User Manual E-20 © National Instruments Corporation To use the error interrupt, set the ERRINTEN bit in the Command Register 3. If this bit is set, an interrupt is generated whenever the OVERFLOW or the OVERRUN bit in the Status Register is set.
Appendix E Register-Level Programming © National Instruments Corporation E-21 Lab-PC+ User Manual updated when a low level is detected on either EXTUPDATE* or OUTA2. If LDAC0 is set low, the analog output from DAC0 is updated as soon as the DAC0 Data Register is written to.
Register-Level Programming Appendix E Lab-PC+ User Manual E-22 © National Instruments Corporation The following formula calculates the voltage output versus digital code for a bipolar analog output configuration and two’s complement coding: V out = 5.
Appendix E Register-Level Programming © National Instruments Corporation E-23 Lab-PC+ User Manual 3. Enable timer interrupts. Timer interrupts refer to the interrupts generated by rising edges on OUTA2 or EXTUPDATE*. A rising edge on OUTA2 or EXTUPDATE* sets the CNTINT bit high in the Status Register.
Register-Level Programming Appendix E Lab-PC+ User Manual E-24 © National Instruments Corporation D7 D6 D5 D4 D3 D2 D1 D0 Control-W ord Flag 1 = Mode Set Mode Selection 00 = Mode 0 01 = Mode 1 1X = M.
Appendix E Register-Level Programming © National Instruments Corporation E-25 Lab-PC+ User Manual Modes of Operation for the 8255A The three basic modes of operation for the 8255A are as follows: • Mode 0 – Basic I/O • Mode 1 – Strobed I/O • Mode 2 – Bidirectional bus The 8255A also has a single bit set/reset feature for Port C.
Register-Level Programming Appendix E Lab-PC+ User Manual E-26 © National Instruments Corporation Table E -5. Mode 0 I/O Configurations Control Word Group A Group B Bit Port A Port C 1 Port B Port C .
Appendix E Register-Level Programming © National Instruments Corporation E-27 Lab-PC+ User Manual Mode 1 This mode is used for transferring data with handshake signals. Ports A and B use the eight lines of Port C to generate or receive the handshake signals.
Register-Level Programming Appendix E Lab-PC+ User Manual E-28 © National Instruments Corporation Port C status-word bit definitions for input (Port A and Port B): 76 54 32 10 I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB Bit Name Description 7-6 I/O Extra I/O status lines when Port A is in Mode 1 input.
Appendix E Register-Level Programming © National Instruments Corporation E-29 Lab-PC+ User Manual Programming Example Example 1. Configure Port A as an input port in Mode 1: • Write B0 (hex) to the Digital Control Register. • Wait for bit 5 of Port C (IBFA) to be set, indicating that data has been latched into Port A.
Register-Level Programming Appendix E Lab-PC+ User Manual E-30 © National Instruments Corporation Port C status-word bit definitions for output (Port A and Port B): 76 54 32 10 OBFA* INTEA I/O I/O INTRA INTEB OBFB* INTRB Bit Name Description 7 OBFA* Output buffer full for Port A.
Appendix E Register-Level Programming © National Instruments Corporation E-31 Lab-PC+ User Manual Programming Example Example 1. Configure Port A as an output port in Mode 1: • Write A0 (hex) to the Digital Control Register. • Wait for bit 7 of Port C (OBFA*) to be cleared, indicating that the data last written to Port A has been read.
Register-Level Programming Appendix E Lab-PC+ User Manual E-32 © National Instruments Corporation Port B direction 1 = input 0 = output Group B Mode 0 = Mode 0 1 = Mode 1 1 X X 1/0 1 1/0 X 1/0 7 65 4.
Appendix E Register-Level Programming © National Instruments Corporation E-33 Lab-PC+ User Manual At the digital I/O connector, Port C has the following pin assignments when in Mode 2. OBF A* PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 STBA* INTRA IBF A Group A ACKA* I/O I/O I/O Programming Example Example.
Register-Level Programming Appendix E Lab-PC+ User Manual E-34 © National Instruments Corporation Single Bit Set/Reset Feature Any of the 8 bits of Port C can be set or reset with one control word. This feature is used to generate status and control for Port A and Port B when operating in Mode 1 or Mode 2.
© National Instruments Corporation F-1 Lab-PC+ User Manual Appendix F Customer Communication For your convenience, this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation.
Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration.
Lab-PC+ Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item. Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration.
Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: Lab-PC+ User Manual Edition Date: June 1996 Part Number: 320502B-01 Please comment on the completeness, clarity, and organization of the manual.
© National Instruments Corporation Glossary-1 Lab-PC+ User Manual Glossary Prefix Meaning Value p- pico- 10 -12 n- nano- 10 -9 µ - micro- 10 -6 m- milli- 10 -3 k- kilo- 10 3 M- mega- 10 6 G- giga- 1.
Glossary Lab-PC+ User Manual Glossary-2 © National Instruments Corporation NRSE non-referenced single-ended PPI programmable peripheral interface ppm parts per million PS/2 IBM Personal System/2 R EX.
© National Instruments Corporation Index- 1 Lab-PC+ User Manual Index Numbers 2SDAC0 bit, D-9 2SDAC1 bit, D-9 +5 V signal (table), 3-3 8253 Counter/Timer Register Groups A and B, D-23 to D-32 Counter.
Index Lab-PC+ User Manual Index- 2 © National Instruments Corporation A/D Clear Register clearing A/D FIFO, E -7 description, D-18 A/D Configuration Register, E-9 A/D conversion.
Index © National Instruments Corporation Index- 3 Lab-PC+ User Manual input signals, 3-4 Lab -PC+ instrumentation amplifier (figure), 3 -5 analog input specifications, A-1 to A -2 amplifier character.
Index Lab-PC+ User Manual Index- 4 © National Instruments Corporation HWTRIG, 3-21, D -10, E-11, E-13, E-14 INTSCAN, D -14, E-17 to E-19 Lab -PC/PC+, D-7 LDAC0, D-9, E -20 to E-21 LDAC1, 3 -23, D-9, E-20 to E-21 MA<2..0>, D -6 OVERFLOW, D-7, E -20.
Index © National Instruments Corporation Index- 5 Lab-PC+ User Manual PC bus interface, 2-1 factory settings (table), 2-3 parts locator diagram, 2-2 Configuration and Status Register Group, D-4 to D .
Index Lab-PC+ User Manual Index- 6 © National Instruments Corporation D D<7..0> bits A/D FIFO Register, D-17 Counter A0 Data Register, D -24 Counter A1 Data Register, D -25 Counter A2 Data Regi.
Index © National Instruments Corporation Index- 7 Lab-PC+ User Manual Mode 1 output, E-29 to E -31 control words, E -29 Port C pin assignments, E-30 Port C status-word bit definitions, E -30 programm.
Index Lab-PC+ User Manual Index- 8 © National Instruments Corporation EXTUPDATE* signal analog output circuitry programming, E -20 to E-21 data acquisition timing, 3-23 to 3-24 generating interrupts .
Index © National Instruments Corporation Index- 9 Lab-PC+ User Manual differential connection considerations, 3-6 to 3 -9 floating signal sources, 3-8 to 3-9 ground-referenced signal sources, 3-7 to .
Index Lab-PC+ User Manual Index- 10 © National Instruments Corporation disabling DMA transfers (figure), 2-7 factory settings (figure), 2-6 NRSE input, 2-13 PC bus interface factory settings (table),.
Index © National Instruments Corporation Index- 11 Lab-PC+ User Manual N NI -DAQ driver software, 1-2 to 1-3 NRSE input (eight channels) configuration, 2 -13 definition (table), 2-11 signal connectio.
Index Lab-PC+ User Manual Index- 12 © National Instruments Corporation PRETRIG bit controlled acquisition mode posttrigger mode, E-12 pretrigger mode, E-14 data acquisition timing, 3-21 description, .
Index © National Instruments Corporation Index- 13 Lab-PC+ User Manual 8253 Counter/Timer Register Groups A and B, D-23 to D-32 8255A Digital I/O Register Group, D -33 to D-37 Analog Input Register G.
Index Lab-PC+ User Manual Index- 14 © National Instruments Corporation grounded signal sources (NRSE configuration), 3 -11 to 3-12 software programming choices LabVIEW and LabWindows/CVI software, 1-.
Index © National Instruments Corporation Index- 15 Lab-PC+ User Manual general-purpose timing connections, 3-24 to 3 -28 event-counting application with external switch gating (figure), 3-25 frequenc.
Un punto importante, dopo l’acquisto del dispositivo (o anche prima di acquisto) è quello di leggere il manuale. Dobbiamo farlo per diversi motivi semplici:
Se non hai ancora comprato il National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ è un buon momento per familiarizzare con i dati di base del prodotto. Prime consultare le pagine iniziali del manuale d’uso, che si trova al di sopra. Dovresti trovare lì i dati tecnici più importanti del National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ - in questo modo è possibile verificare se l’apparecchio soddisfa le tue esigenze. Esplorando le pagine segenti del manuali d’uso National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ imparerai tutte le caratteristiche del prodotto e le informazioni sul suo funzionamento. Le informazioni sul National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ ti aiuteranno sicuramente a prendere una decisione relativa all’acquisto.
In una situazione in cui hai già il National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+, ma non hai ancora letto il manuale d’uso, dovresti farlo per le ragioni sopra descritte. Saprai quindi se hai correttamente usato le funzioni disponibili, e se hai commesso errori che possono ridurre la durata di vita del National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+.
Tuttavia, uno dei ruoli più importanti per l’utente svolti dal manuale d’uso è quello di aiutare a risolvere i problemi con il National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+. Quasi sempre, ci troverai Troubleshooting, cioè i guasti più frequenti e malfunzionamenti del dispositivo National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ insieme con le istruzioni su come risolverli. Anche se non si riesci a risolvere il problema, il manuale d’uso ti mostrerà il percorso di ulteriori procedimenti – il contatto con il centro servizio clienti o il servizio più vicino.
