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Intel ® 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR Datasheet January 2002 Docum ent Number : 290725-002 R.
R 2 Intel ® 82845 MCH for SDR Datasheet Information in this document i s provided in connection with Intel ® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
R Intel ® 82845 MCH for SDR Datasheet 3 Contents 1 Introduction ................................................................................................................... ..... 11 1.1 Term inology and Notations ..............................
R 4 Intel ® 82845 MCH for SDR Datasheet 3.5 Host-Hub Interf ace Bridge Devic e Registers (Devic e 0) ...................................... 43 3.5.1 VID—Vendor Identific ation Register (Devic e 0) .................................... 45 3.5.2 DID—Device Identific ation Register (Devic e 0) .
R Intel ® 82845 MCH for SDR Datasheet 5 3.6.11 SBUSN1—Secondary Bus Number Regis ter (Device 1) ...................... 86 3.6.12 SUBUSN1—Subordinate Bus Num ber Register (Device 1).................. 86 3.6.13 SMLT1—Sec ondary Master Latency Tim er Register (Device 1) .
R 6 Intel ® 82845 MCH for SDR Datasheet 5.3 AGP Interface O verview ..................................................................................... 112 5.3.1 AGP Target O perations ...............................................................
R Intel ® 82845 MCH for SDR Datasheet 7 Figures Figure 1. Intel ® MCH Sim plified Block Diagram ................................................................. 20 Figure 2. PAM Register Attributes ..................................................
R 8 Intel ® 82845 MCH for SDR Datasheet Revision History Revision Number Description Date -001 Initi al Releas e. Septem ber 2001 -002 • Changed the docum ent nam e to add the t erm “f or S DR”. • DW TC—DRAM W rite Therm al Managem ent Control Regis t er was incorrec t l y pl ac ed in Device 0.
R Intel ® 82845 MCH for SDR Datasheet 9 Intel ® 82845 MCH Features ! Intel ® Pentium ® 4 Process or (478 pin packag e) Support Enhanced Mode Scaleable Bus Protocol 2x Address, 4x Data .
R 10 Intel ® 82845 MCH for SDR Datasheet System Block Diagram Inte l ® 82801BA I/O C o ntro lle r H u b (IC H 2 ) Sys t e m Memo r y sys_blk PCI Bu s Inte l ® 82845 Memo r y C on troller H ub (MCH) 4x AG P Graphi cs Co nt ro ll er Hub Inte rfa ce 4 US B Por t s; 2 HC Ultra A TA /1 00 AC '97 Codec(s) (op tio n a l) AC' 97 2.
Introduction R Intel ® 82845 MCH for SDR Datasheet 11 1 Introduction The In tel ® 82845 Memory Controller Hu b (MCH) is des ign ed for us e w ith the Int el ® Pentium ® 4 processor in the 478-pi n packag e.
Introduction R 12 Intel ® 82845 MCH for SDR Datasheet Term Description GART Graphics A pert ure Re-map Table. This tabl e c ontains t he page re-map inf ormat i on us ed during AGP apert ure addres s trans l at ions. GTLB Graphics Trans lation Look -as ide Buff er.
Introduction R Intel ® 82845 MCH for SDR Datasheet 13 1.2 Reference Documents Document Do cument Number / Location Intel ® Pentium 4 Process or i n a 478 P in Pack age and Intel ® 845 Chi ps et Pla.
Introduction R 14 Intel ® 82845 MCH for SDR Datasheet 1.3 Intel ® 845 Chipset Sy stem A rchitecture The MCH provides th e processor interf ace, sys tem mem ory interface, A GP interface, and h ub interface in an 845 chipset des ktop platform .
Introduction R Intel ® 82845 MCH for SDR Datasheet 15 1.4.1 Sy stem Bus Interface The MCH is optim ized for the Pentium 4 processor. The primary enhancem ents over the Com patible Mode P6 bu s protoc.
Introduction R 16 Intel ® 82845 MCH for SDR Datasheet 1.4.3 Sy stem Memory Interface The MCH directly s upports on e chann el of PC133 SDRA M. The m emory interface supports Single Data R ate (SDR) devices w ith dens ities of 64 Mb, 128 Mb, 256 Mb, an d 512 Mb technology .
Introduction R Intel ® 82845 MCH for SDR Datasheet 17 1.4.5 Hub Interface The 8-bit hub interf ace connects the MCH to the IC H2. All com m unication betw een the MCH an d the ICH2 occurs over the h ub interface. The h ub interface ru ns at 66 MHz / 266 MB/s.
Introduction R 18 Intel ® 82845 MCH for SDR Datasheet 1.4.7 Sy stem Interrupts The MCH su pports both Intel 8259 an d Penti um 4 processor in terru pt delivery mechani sm s.
Signal Description R Intel ® 82845 MCH for SDR Datasheet 19 2 Signal Description This chapter provides a d e tailed d escription of the MCH signals. The signal descriptions are arranged in fun ctional groups according to th eir associated interf ace (see Figure 1).
Signal Description R 20 Intel ® 82845 MCH for SDR Datasheet Figure 1. Intel ® MCH Simplified Block Diagram bl ock_di a_845 SCS[ 11: 0]# SMA[12 : 0] SBS[ 1: 0] SRAS# SCAS# SWE# SDQ[6 3:0 ] SCB[ 7: 0].
Signal Description R Intel ® 82845 MCH for SDR Datasheet 21 2.1 Sy stem Bus Signals Signal Nam e Ty pe Description ADS# I/O AGTL+ A ddress S trobe: The syst em bus owner assert s ADS# t o indicat e t he f irst of two cycles of a request phas e.
Signal Description R 22 Intel ® 82845 MCH for SDR Datasheet Signal Nam e Ty pe Description HD[63:0]# I /O AGTL+ Host Data: Thes e s ignals are c onnec ted to t he s ystem data bus. HD[63:0]# are t ransferred at a 4x rate. Not e that t he dat a s ignals are inverted on the s ystem bus.
Signal Description R Intel ® 82845 MCH for SDR Datasheet 23 2.2 SDR SDRA M Interface Signals Signal Nam e Ty pe Description SCS[11: 0]# O CMOS Chip Sele ct: These signals s elect t he particul ar S DRAM com ponent s during the act ive stat e. Note: There are two SCS# s i gnal s per SDRAM row.
Signal Description R 24 Intel ® 82845 MCH for SDR Datasheet 2.4 A GP Interface Signals 2.4.1 AGP A ddressing Signals Signal Nam e Ty pe Description PIPE# I AGP Pipelined Read: This si gnal i s assert ed by the AGP m ast er t o indicat e a full-width address is t o be enqueued on by t he target us i ng t he A D bus.
Signal Description R Intel ® 82845 MCH for SDR Datasheet 25 2.4.2 A G P Fl ow Control Signal s Signal Nam e Ty pe Description RBF# I AGP Read Buffer Full: RB F# i ndi c ates if the m as ter is ready t o ac cept previously reques t ed l ow priorit y read dat a.
Signal Description R 26 Intel ® 82845 MCH for SDR Datasheet 2.4.4 AGP Strobes Signals Signal Nam e Ty pe Description AD_STB0 I/ O (s/t/s) AGP A ddress/ Data Bus Strobe-0: This signal provi des tim ing for 2x and 4x data on AD[15: 0] and the C/B E [ 1:0]# s i gnal s .
Signal Description R Intel ® 82845 MCH for SDR Datasheet 27 Signal Nam e Ty pe Description G_DEVSEL # I/O s/t/s AGP Device Select: This s i gnal i ndi c ates that a FRAME#-based AG P t arget device has dec oded its addres s as t he t arget of t he c urrent acc es s.
Signal Description R 28 Intel ® 82845 MCH for SDR Datasheet 2.5 Clocks, Reset, and Miscellaneous Signals Signal Nam e Ty pe Description BCLK BCLK# I CMOS Differential Host Clock I n : These pins rec eive a different ial host c lock from t he external clock synthes i zer.
Signal Description R Intel ® 82845 MCH for SDR Datasheet 29 2.6 Voltage Reference and Pow er Signals Signal Nam e T y pe Description HVREF Ref Host Reference Voltage: Ref erence voltage i nput for the dat a, address, and com m on cloc k signal s of the hos t A GTL+ interfac e.
Signal Description R 30 Intel ® 82845 MCH for SDR Datasheet 2.7 Reset States During Reset Z Ti-state ISO Isolate inputs in inactive st ate S Strap i nput sam pled du ring as serti on or on th e de-as.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 31 3 Register Description The MCH contains tw o sets of s oftw are accessi ble registers , accessed via th e host process or I/O address space: • Control regis ters I/O m apped into th e processor I/O space, w hich control access to PCI an d AGP conf iguration s pace (see Section 3.
Register Desc ription R 32 Intel ® 82845 MCH for SDR Datasheet Term Description Reserved Registers In addition to res e rved bi t s within a regist er, the MCH cont ai ns address l oc ations i n the configurat ion space t hat are m ark ed “Reserved”.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 33 3.2.1 Standard PCI Bus Configuration M echanism The PCI Bus defin es a slot based "conf igu ration space" that allow s each dev ice to contain up to 8 fun ctions w ith each function containi ng u p to 256 8-bit config uration reg isters.
Register Desc ription R 34 Intel ® 82845 MCH for SDR Datasheet Primary PCI and Downst ream Conf iguration M echani sm If the Bus Num b er in the CONF_ADDR is n on-zero, and is less than the v alue in.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 35 Bit Descripti ons 31 C onfiguration Enable (CFGE) . 0 = Disable. 1 = Enable. A c cess es to PCI c onfigurati on s pace are enabled. 30:24 Reserved. Thes e bi t s are read only and have a value of 0.
Register Desc ription R 36 Intel ® 82845 MCH for SDR Datasheet 3.3.2 CONF_DAT A —Configuration Data Register I/O Address : 0CFCh Default Value: 00000000h Access: R /W Size: 32 bits CONF_DATA is a 32 bit read/w rite wi ndow into conf iguration space.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 37 3.4.1 DRAMWIDTH—DRA M Width Register Address O ffs et: 2Ch Default Value: 00h Access: R /W Size: 8 bits This register determ ines the w idth of SDRA M devices popu lated in each row of mem ory .
Register Desc ription R 38 Intel ® 82845 MCH for SDR Datasheet 3.4.2 DQCMDSTR—Str ength Contr ol Register (SDQ and CM D Signal Groups) Memor y Address O ffs et: 30h Default Value: 00h Access: R /W Size: 8 bits This register controls the drive strength of the I/O buff ers for the DQ/DQS and CMD signal groups .
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 39 3.4.3 CKESTR—Strength Control Regi ster (SCKE Signal Gr oup) Memor y Address O ffs et: 31h Default Value: 00h Access: R /W Size: 8 bits This register controls the drive strength of the I/O buff ers for the CKE signal g roup.
Register Desc ription R 40 Intel ® 82845 MCH for SDR Datasheet 3.4.4 CSBSTR—Strength Control Regi ster (SCS# Signal Gr oup) Memor y Address O ffs et: 32h Default Value: 00h Access: R /W Size: 8 bits This register controls the drive strength of the I/O buffers f or the SCS# signal group.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 41 3.4.5 CKSTR—Strength Control Regi ster (Clock Signal Gr oup) Memor y Address O ffs et: 33h Default Value: 00h Access: R /W Size: 8 bit.
Register Desc ription R 42 Intel ® 82845 MCH for SDR Datasheet 3.4.6 RCVENSTR—Strength Control Regi ster (RCVENOUT Signal Gr oup) Memor y Address O ffs et: 34h Default Value: 00h Access: R /W Size: 8 bits This register con trols the driv e streng th of th e I/O buff ers for the R eceive Enable Ou t sign al group (RDCLKO# signal).
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 43 3.5 Host-Hub Interface Bridge Dev ice Registers (Dev ice 0) Table 8 provides the regis ter address m ap for Device 0 PCI config uration space. A n “ s” in the Default Value colum n indicates that a strap determines the pow er-up default v alue for that bit.
Register Desc ription R 44 Intel ® 82845 MCH for SDR Datasheet A ddress Offset Register Sy mbol Register Name Default Value A ccess 87–8Bh — Reserved.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 45 3.5.1 VID—Vendor Identi fi cati on Regi ster (Device 0) Address O ff set: 00–01h Default Value: 8086h Attribute: RO Size: 16 bits The VID Register contains the v endor identification num ber.
Register Desc ription R 46 Intel ® 82845 MCH for SDR Datasheet 3.5.3 PCICM D—PCI Command Register (Device 0) Address O ff set: 04–05h Default: 0006h Access: R /W , RO Size 16 bits Since MCH Devi ce 0 does not phy sically reside on PCI0, man y of the bits are n ot implem ented.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 47 3.5.4 PCISTS—PCI Status Register (Device 0) Address O ff set: 06–07h Default Value: 0090h Access: R O, R /W C Size: 16 bits PCISTS is a 16-bit statu s regist er that reports the occu rrence of error ev ents on Device 0s on the hub interf ace.
Register Desc ription R 48 Intel ® 82845 MCH for SDR Datasheet 3.5.5 RID—Revision Identification Register (Device 0) Address O ff set: 08h Default Value: See table below Access: R O Size: 8 bits This register con tains th e revisi on num ber of the MCH Device 0.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 49 3.5.8 M LT—M aster Latency Timer Register (Device 0) Address O ffs et: 0Dh Default Value: 00h Access: R O Size: 8 bits The hub interf ace does not com prehend the con cept of Master L atency Timer.
Register Desc ription R 50 Intel ® 82845 MCH for SDR Datasheet 3.5.10 A PBA SE—Aperture Base Configuration Register (Dev ice 0) Off set: 10–13h Default: 0000_0008h Access: R /W , RO Size: 32 bits The APBASE is a stan dard PCI Base Addres s regist er that is us ed to set the base of the Graphics Aperture.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 51 3.5.11 SVID—Subsy stem Vendor I dentification (Device 0) Off set: 2C–2Dh Default: 0000h Access: R /W O Size: 16 bits This value is used to identify the vendor of the subsy stem . Bit Descripti on 15:0 Subsy stem Vendor ID.
Register Desc ription R 52 Intel ® 82845 MCH for SDR Datasheet 3.5.14 A GPM —A GP Mi scel l aneous Configurati on Regi ster (Device 0) Address O ff set: 51h Default Value: 00h Access: R /W Size: 8 bits Bit Descripti ons 7:2 Reserved. 1 A perture A ccess Gl obal Enable (APEN).
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 53 3.5.16 DRA —DRA M Row Attribute Registers (Dev ice 0) Off set: 70–73h (DRA0–DRA3) Default: 00h Access: R /W Size: 8 bits The DRAM Row Attribute Regis ter defin es the page s izes to be us ed w hen access ing dif ferent pairs of row s.
Register Desc ription R 54 Intel ® 82845 MCH for SDR Datasheet Bit Descripti on 7 Reserved. 6:4 Row A ttribute for Odd -Nu m b ered Ro w (RA ODD). This 3-bit field def i nes the page size of the corresponding row. 001 = 2 KB 010 = 4 KB 011 = 8 KB 100 = 16 KB Others = Res erved 3 Reserved.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 55 3.5.17 DRT—DRA M Timing Register (Device 0) Off set: 78–7Bh Default: 00000010h Access: R /W Size: 32 bits Bit Descripti on 31:19 Reserved.
Register Desc ription R 56 Intel ® 82845 MCH for SDR Datasheet 3.5.18 DRC—DRA M Controll er M ode Register (Devi ce 0) Off set: 7C–7Fh Default: 00000000h Access: R /W , RO Size: 32 bits Bit Descripti on 31:30 Revision Number (REV)—R/W . Refl ec ts t he revision num ber of the f ormat us ed for SDRA M register def inition.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 57 Bit Descripti on 6:4 Mode Select (SM S )—R/W . These bit s selec t t he speci al operat i onal m ode of t he s ystem mem ory interf ac e. The spec i al m odes are int ended for init i al i zat i on at power up.
Register Desc ription R 58 Intel ® 82845 MCH for SDR Datasheet 3.5.19 DERRSYN—DRA M Error Sy ndrome Register (Device 0) Address O ff set: 86h Default Value: 00h Access: R O Size: 8 bits This regist er is used to report th e ECC sy ndromes f or each quadw ord of a 32 byte-alig ned data quantity read from th e system memory array.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 59 3.5.21 PA M[0:6]—Programmable A ttribute Map Registers (Device 0) Address O ff set: 90–96h (PAM0–PAM6) Default Value: 00h Attribut.
Register Desc ription R 60 Intel ® 82845 MCH for SDR Datasheet At the tim e that a hub interface or A GP accesses to the PA M region m ay occur, the targeted PA M segm ent mu st be program med to be both readabl e and w riteable. As an ex ample, cons ider BIOS that is implem ented on the expansion bu s.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 61 Table 9. PAM Regist er A ttributes PA M Reg A ttribute Bits Memory Segment Comments Offset PAM0[3:0] Reserved 90h PAM0[7:4] R R W E RE 0.
Register Desc ription R 62 Intel ® 82845 MCH for SDR Datasheet Extended System BIOS A rea (E0000h–EFFFFh) This 64 KB area is d ivided into four 16 KB segments th at can be assigned w ith diff erent attributes via PAM con trol regist er as defin ed by th e table above.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 63 3.5.23 SM RAM—Sy stem M anagement RA M Control Register (Device 0) Address O ffs et: 9Dh Default Value: 02h Access: R/W , RO, R/W /L Size: 8 bits The SMRAMC reg ister cont rols how accesses to Compatible an d Extended SMRA M spaces are treated.
Register Desc ription R 64 Intel ® 82845 MCH for SDR Datasheet 3.5.24 ESM RAMC—Extended Sy stem M gmt RA M Control Register (Device 0) Address O ff set: 9Eh Default Value: 38h Access: RO, R/W , R/W C, R/W /L Size: 8 bits The Extended SMRA M register con trols the con figu ration of Ex tended SMRAM s pace.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 65 3.5.25 A CA PID—A GP Capability Identifier R egister (Dev ice 0) Address O ff set: A0–A3h Default Value: 0020_0002h Access: R O Size: 32 bits This register provides standard identifier for AGP capability.
Register Desc ription R 66 Intel ® 82845 MCH for SDR Datasheet 3.5.26 A GPSTA T—A GP Status Register (Device 0) Address O ff set: A4–A7h Default Value: 1F00_0217h Access: R O Size: 32 bits This register reports AGP device capability/status. Bit Descripti on 31:24 Request Queue (RQ).
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 67 3.5.27 A GPCMD—A GP Command Register (Device 0) Address O ff set: A8–ABh Default Value: 0000_0000h Access: R /W Size: 32 bits This register provides control of the AGP operational parameters.
Register Desc ription R 68 Intel ® 82845 MCH for SDR Datasheet 3.5.28 A GPCTRL—A GP Control Register (Device 0) Address O ff set: B0–B3h Default Value: 0000_0000h Access: R /W Size: 32 bits This register provides for additional control of the AGP interface.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 69 3.5.29 A PSIZE—A perture Size (Device 0) Address O ff set: B4h Default Value: 00h Access: R /W Size: 8 bits This register determ ines the effectiv e size of th e Graphics A perture used f or a particular MCH config uration.
Register Desc ription R 70 Intel ® 82845 MCH for SDR Datasheet 3.5.30 A TTBA SE—Ap erture Translation Table Base Register (Device 0) Address O ff set: B8–BBh Default Value: 0000_0000h Access: R /W Size: 32 bits This register prov ides the st arting address of the Graph ics Apertu re Translation Table Base located in the sy stem m emory .
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 71 3.5.31 A MTT—A GP Interface Multi-Transaction Timer Register (Device 0) Address O ff set: BCh Default Value: 00h Access: R /W Size: 8 .
Register Desc ription R 72 Intel ® 82845 MCH for SDR Datasheet 3.5.32 LPTT—A GP Low Priority Transaction Timer Register (Device 0) Address O ff set: BDh Default Value: 00h Access: R /W Size: 8 bits LPTT is an 8-bit register sim ilar in fu nction to AMTT.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 73 3.5.33 TOM—Top of Low Memory Register (Device 0) Address O ffs et: C4–C5h Default Value: 0100h Access: R /W Size: 16 bits This register con tains th e m axim um address below 4 GB that should be treated as a m em ory access.
Register Desc ription R 74 Intel ® 82845 MCH for SDR Datasheet 3.5.34 MCHCFG—M CH Configur ati on Regi ster (Device 0) Off set: C6–C7h Default: 0000h Access: R /W , RO Size: 16 bits Bit Descripti on 15:12 Reserved. 11 System Memory Frequency S elect.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 75 3.5.35 ERRSTS—Error Status Register (Device 0) Address O ffs et: C8–C9h Default Value: 0000h Access: R /W C Size: 16 bits This register is used to report various error conditions via the hub interf ace m essages to ICH2.
Register Desc ription R 76 Intel ® 82845 MCH for SDR Datasheet Bit Descripti on 0 Si n g l e-bit DRAM ECC Error Flag (DS ERR). 0 = Sof tware must write a 1 t o clear thi s bit and unloc k the error logging m echanis m. 1 = A m em ory read dat a transf er had a s ingle-bit c orrectable error and t he correct ed dat a was sent f or t he ac cess .
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 77 Bit Descripti on 4 SERR on A GP A ccess Outside of Graphics A perture (OOGF_SERR). 0 = Disable. 1 = Enable. Generat i on of the hub interf ac e SERR m essage i s enabled when an AGP acc es s occurs t o an address out s ide of the graphi c s aperture.
Register Desc ription R 78 Intel ® 82845 MCH for SDR Datasheet 3.5.37 SM ICM D—SM I Command Register (Device 0) Address Off set: CC–CDh Default Value: 0000h Access: R /W Size: 16 bits This register en ables variou s errors to gen erate a SMI mes sage v ia the hu b interface.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 79 3.5.39 SKPD—Scratchpad Data Register (Device 0) Address O ffs et: DE–DFh Default Value: 0000h Access: R /W Size: 16 bits Bit Descripti on 15:0 Scratchpad [15:0]. These bits are R/W s t orage bi t s that have no ef fect on t he MCH funct ionality.
Register Desc ription R 80 Intel ® 82845 MCH for SDR Datasheet 3.6 Bridge Registers (Dev ice 1) Table 10. provides the regis ter address m ap for Device 0 PCI config uration space. A n “ s” in the Default Value colum n indicates that a strap determines the pow er-up default v alue for that bit.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 81 A ddress Offset S y mbol Name Default A ccess 58–5Fh DRTC DRA M Read Therm al Management Cont rol 0000000 0h R/W /L 59–FFh — Reserved — — 3.
Register Desc ription R 82 Intel ® 82845 MCH for SDR Datasheet 3.6.3 PCICM D1—PCI-PCI Command Register (Device 1) Address O ff set: 04–05h Default: 0000h Access: R O, R /W Size 16 bits Bit Descripti ons 15:10 Reserved. 9 Fast Back-to-Back (FB2B)—RO.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 83 3.6.4 PCISTS1—PCI-PCI Status Register (Device 1) Address O ff set: 06–07h Default Value: 00A0h Access: R O, R /W C Size: 16 bits PCI.
Register Desc ription R 84 Intel ® 82845 MCH for SDR Datasheet 3.6.5 RID1—Revision Identification Register (Device 1) Address O ff set: 08h Default Value: See RID1 table below Access: R O Size: 8 bits This register con tains th e revisi on num ber of the MCH device 1.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 85 3.6.8 M LT1—M aster Latency Timer Register (Device 1) Address O ffs et: 0Dh Default Value: 00h Access: R /W Size: 8 bits This functionality is not applicable.
Register Desc ription R 86 Intel ® 82845 MCH for SDR Datasheet 3.6.11 SBUSN1—Secondary Bus Number Regi ster (Device 1) Off set: 19h Default: 00h Access: R /W Size: 8 bits This register identifies the bus nu mber assign ed to the second bus side of the “virtual” PCI-PCI bridge i.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 87 3.6.13 SMLT1—Secondary Master Latency Timer Register (Device 1) Address O ff set: 1Bh Default Value: 00h Access: R /W Size: 8 bits This register controls the bus tenure of th e MCH on AGP.
Register Desc ription R 88 Intel ® 82845 MCH for SDR Datasheet 3.6.14 IOBA SE1—I/O Base A ddress Register (Device 1) Address O ffs et: 1Ch Default Value: F0h Access: R /W Size: 8 bits This register.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 89 3.6.16 SSTS1—Secondary PCI-PCI Status Register (Device 1) Address O ff set: 1E–1Fh Default Value: 02A0h Access: R O, R /W C Size: 16 bits SSTS1 is a 16 -bit status register th at reports the occurrence of error conditions associated with secondary side (i.
Register Desc ription R 90 Intel ® 82845 MCH for SDR Datasheet 3.6.17 M BASE1—Memory Base A ddress Register (Device 1) Address O ff set: 20–21h Default Val u e: FFF0h Access: R /W Size: 16 bits T.
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 91 3.6.19 PM BASE1—Prefetchable Memory Base A ddress Register (Device 1) Address O ff set: 24–25h Default Val u e: FFF0h Access: R /W S.
Register Desc ription R 92 Intel ® 82845 MCH for SDR Datasheet 3.6.21 BCTRL1—PCI-PCI Bridge Control Register (Device 1) Address O ff set: 3Eh Default: 00h Access: R O, R /W Size 8 bits This register prov ides exten sions to th e PCICMD1 regis ter that are specif ic to PCI-PCI bridges .
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 93 Bit Descripti ons 0 Parity Error Response Enable (PER_EN)—R/ W . Cont rols MCH’s res ponse to dat a phas e parity errors on AGP . 0 = Addres s and data pari t y errors on AGP are not report ed via the MCH hub interf ace SERR# mess aging mec hanis m.
Register Desc ription R 94 Intel ® 82845 MCH for SDR Datasheet 3.6.23 DWTC—DRA M Wri te Ther mal M anagement Control Register (Device 1) Address O ff set: 50–57h Default Value: 00h Access: R /W /L Size: 64 bits Bit Descripti ons 63:41 Reserved. 40:28 Global Write Hexword Threshold (GWHT).
Register Desc ription R Intel ® 82845 MCH for SDR Datasheet 95 3.6.24 DRTC—DRA M Read Thermal M anagement Control Register (Device 1) Address O ff set: 58–5Fh Default Value: 0000_0000_0000_0000h Access: R /W /L Size: 64 bits Bit Descripti ons 63:41 Reserved.
Register Desc ription R 96 Intel ® 82845 MCH for SDR Datasheet This page is intentionally left blank..
System Addres s Map R Intel ® 82845 MCH for SDR Datasheet 97 4 System Address M ap A sy stem based on the 845 chips et supports 4 GB of address able m emory space and 64 KB+3 of addressable I/O space. The I/O and m emory s paces are divided by sy stem configuration s oftw are into region s.
System Addres s Map R 98 Intel ® 82845 MCH for SDR Datasheet Figure 4. DOS Comp atible A rea A ddress Map M onochrom e Display Adapter S pace Up per, Lower, Expans ion Card BIOS and Buffer Area 1 M B.
System Addres s Map R Intel ® 82845 MCH for SDR Datasheet 99 4.1.1 VGA and MDA M emory Space Video cards use th ese legacy address ranges to m ap a fram e buffer or a character- based video buff er.
System Addres s Map R 100 Intel ® 82845 MCH for SDR Datasheet 4.1.2 PAM Memory Spaces The address ranges in this m emory space are: • PAMC0 0_000C_0000 to 0_000C_3FFF • PAMC4 0_000C_4000 to 0_000.
System Addres s Map R Intel ® 82845 MCH for SDR Datasheet 101 4.1.4 TSEG SM M M emory Space The TSEG SMM space (T OM – T SEG to TOM) allows sy stem m anagement softw are to p artition a region of sy stem m em ory just below the top of low mem ory (TOM) that is acces sible only by sy stem manage men t sof tw are.
System Addres s Map R 102 Intel ® 82845 MCH for SDR Datasheet 4.1.8 AGP A perture Space (Device 0 BA R) Pr o cesso rs and AGP d evice s c ommunicate thr ough a sp ecia l buffe r call e d the “gr aphi c s ape r ture ” (APBASE to A PBASE + APSIZE).
System Addres s Map R Intel ® 82845 MCH for SDR Datasheet 103 4.2.1 AGP DRA M Graphics Ap erture Memory -mapped, graphi cs data structu res can res ide in a Graphics Aperture to s ys tem m emory. This aperture is an addres s rang e defined by the APBASE and A PSIZE registers of the MC H device 0.
System Addres s Map R 104 Intel ® 82845 MCH for SDR Datasheet 4.3.1 SM M Space Definition Its addressed SMM space an d its DRA M SMM space defin e SMM space. The addressed SMM space is defin ed as the ran ge of bu s addresses used by the proces sor to access SMM space.
System Addres s Map R Intel ® 82845 MCH for SDR Datasheet 105 4.4 I/O A ddress Space The MCH does not support th e exis tence of any other I/O devices bes ide itself on th e sy stem bus . The MCH generates eith er hub in terface or AGP bus cycles for all processor I/O access es.
System Addres s Map R 106 Intel ® 82845 MCH for SDR Datasheet 4.5.2 AGP Interface Decode Rules Cycles Initiate d Usi ng AGP FRA ME# Prot ocol The MCH does not support an y AGP FRA ME# access targetin g the h ub interface.
Functional Desc ription R Intel ® 82845 MCH for SDR Datasheet 107 5 Functional Description This chapter describes th e sy stem bus that con nects th e MCH to the processor, th e sy stem mem ory interface, th e AGP interface, th e MCH pow er and therm al managem ent, the MCH clocking , and the MCH sy stem reset an d power s equencin g.
Functional Desc ription R 108 Intel ® 82845 MCH for SDR Datasheet 5.1.2 Sy stem Bus Interrupt Delivery The Pentiu m 4 proces sor su pports th e sy stem bus interru pt deliv ery; the A PIC serial bu s in terrupt delivery mechanis m i s not s upported.
Functional Desc ription R Intel ® 82845 MCH for SDR Datasheet 109 5.2 Sy stem Memory Interface The 845 chipset can be conf igu red to su pport PC133 SDR AM.
Functional Desc ription R 110 Intel ® 82845 MCH for SDR Datasheet 5.2.2.1 Configurat ion Mechanism For DIMMs Detection of the t ype of SDRA M ins talled on t he DIMM is s upported v ia a Serial Pres ence Detect mech anism as defi ned in the JEDEC 168- pin DIMM specification .
Functional Desc ription R Intel ® 82845 MCH for SDR Datasheet 111 5.2.3 M emory Address Translation and Decoding The 845 MCH contains address decoders th at translate th e address receiv ed on the s ys tem bu s or the hub in terface. Decoding and translation of thes e addresses v ary w ith the four SDRA M types .
Functional Desc ription R 112 Intel ® 82845 MCH for SDR Datasheet 5.2.4 DRAM Performance Description The overall m emory perform ance is controlled by the DRA M Timin g (DRT) Regis ter, pipelining depth used in the MCH, m emory speed g rade, and the ty pe of SDRA M used in the sy stem.
Functional Desc ription R Intel ® 82845 MCH for SDR Datasheet 113 Table 15. A GP Commands Supported by the Intel ® MCH When A cting as an AGP Target MCH Host Bri dge AG P Comman d C/BE[3: 0]# Encodi.
Functional Desc ription R 114 Intel ® 82845 MCH for SDR Datasheet 5.3.2 AGP Transaction Ordering The MCH observ es trans action orderin g rul es as def ined by the AGP Interface Sp ecification, Revision 2.0 . 5.3.3 AGP Signal Lev els The 4x data tran sfers use 1.
Functional Desc ription R Intel ® 82845 MCH for SDR Datasheet 115 Table 16. Data Rate Control Bits A GPCNTL .FWCE AG P C M D . FWPE AG P C M D . DRA TE [bit 2 ] AG P C M D . DRA TE [bit 1 ] AG P C M D . DRA TE [bit 0 ] MCH =>AGP Master W ri te Protocol 0 0 X X X 1x 1 1 0 0 1 1x 1 1 0 1 0 2x strobing 1 1 1 0 0 4x strobing 5.
Functional Desc ription R 116 Intel ® 82845 MCH for SDR Datasheet C/BE[3: 0]# Intel ® MCH PCI Comma nd Encoding Cy cle Destination Response as a FRA ME# Targ et Dual Address Cycle 1101 N/A No res po.
Functional Desc ription R Intel ® 82845 MCH for SDR Datasheet 117 MCH Retry/Disconnect Condi t ions The MCH generates retry /disconnect according to th e AGP Interface Specificatio n , Revisio n 2.0 rules w hen being accessed as a target from the AGP FRAME# device.
Functional Desc ription R 118 Intel ® 82845 MCH for SDR Datasheet 5.4.2 Sleep State Control • S0 (Awake): In this state all pow er planes are activ e.
Electrical Char acteristic s R Intel ® 82845 MCH for SDR Datasheet 119 6 Electrical Characteristics This chapter contain s the absolute m aximum operating ratings, pow er characteristics, and DC characteris tics f or the 82845 MCH. 6.1 A bsolute Maximum Ratings Table 1 8 lists the MCH’s m axim um environm ental stress ratings .
Electrical Char acteristic s R 120 Intel ® 82845 MCH for SDR Datasheet 6.3 Signal Groups The signal description includes the ty pe of buffer us ed for the particular signal: AGTL+ Open Drain AGTL+ interface s ignal. Ref er to the A GTL+ I/O Specification f or complete details.
Electrical Char acteristic s R Intel ® 82845 MCH for SDR Datasheet 121 Signal Group Signal Ty pe Signals (s) 1.5 V Core and A GP Voltage VCC1_5 (t) 1.
Electrical Char acteristic s R 122 Intel ® 82845 MCH for SDR Datasheet 6.4 DC Characteristics Table 21. DC Ch aracteristics Symbol Signal Group Paramete r Min Ty p Max Unit Note s I/O Buffer Supply Voltage VCCSM (u) P C133 SDRA M I /O Voltage 3.135 3.
Electrical Char acteristic s R Intel ® 82845 MCH for SDR Datasheet 123 Symbol Signal Group Paramete r Min Ty p Max Unit Note s C I/0 (k,m,p) Input Capacitance 4.65 5.37 pF 1.5 V Interface V IL (e,f) Input Low Voltage 0.4 x VCC1_5 V V IH (e,f) Input High Voltage 0.
Electrical Char acteristic s R 124 Intel ® 82845 MCH for SDR Datasheet This page is intentionally left blank..
Ballout and Package Information R Intel ® 82845 MCH for SDR Datasheet 125 7 Ballout and Package Information This chapter provides the MCH ballo ut and package information. The ballout footprint is show n in Figure 6 and Fig ure 7. These f igures repres ent the ballou t organi zed by ball n um ber.
Ballout and Package Information R 126 Intel ® 82845 MCH for SDR Datasheet Figure 6. Intel ® 82845 MCH Ballo ut Diagram (T op View —Left Side) 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AJ VSS VC.
Ballout and Package Information R Intel ® 82845 MCH for SDR Datasheet 127 Figure 7. Intel ® 82845 MCH Ballo ut Diagram (T op View —Right Side) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VSS VSS VSS VSS VSS .
Ballout and Package Information R 128 Intel ® 82845 MCH for SDR Datasheet Table 22. In tel ® 82845 MCH Ballo ut Listed Alphabetically by Signal Name Signal Name Ball # 66IN P22 AD_STB0 R24 AD_STB0# .
Ballout and Package Information R Intel ® 82845 MCH for SDR Datasheet 129 Signal Name Ball # HA6# U3 HA7# R3 HA8# P7 HA9# R2 HA10# P4 HA11# R6 HA12# P5 HA13# P3 HA14# N2 HA15# N7 HA16# N3 HA17# K4 HA.
Ballout and Package Information R 130 Intel ® 82845 MCH for SDR Datasheet Signal Name Ball # HD44# AH11 HD45# AG12 HD46# AE13 HD47# AF12 HD48# AG13 HD49# AH13 HD50# AC14 HD51# AF14 HD52# AG14 HD53# A.
Ballout and Package Information R Intel ® 82845 MCH for SDR Datasheet 131 Signal Name Ball # SBA4 AE28 SBA5 AE27 SBA6 AE24 SBA7 AE25 SB_STB AF27 SB_STB# AF26 SBS0 F17 SBS1 G17 SCAS# J25 SCK0 F13 SCK1.
Ballout and Package Information R 132 Intel ® 82845 MCH for SDR Datasheet Signal Name Ball # SDQ33 E28 SDQ34 C28 SDQ35 D27 SDQ36 B27 SDQ37 F25 SDQ38 C25 SDQ39 E24 SDQ40 C24 SDQ41 E23 SDQ42 D22 SDQ43 .
Ballout and Package Information R Intel ® 82845 MCH for SDR Datasheet 133 Signal Name Ball # VSS A3, A7, A 11, A15, A 19, A23, A27, D5, D9, D13, D17, D21, E1, E4, E 26, E29, F8, F12, F16, F20, F24, G.
Ballout and Package Information R 134 Intel ® 82845 MCH for SDR Datasheet 7.1 Package Mechanical Information This section provides th e MCH packag e mech anical di men sions . The package is a 593 bal l FC-BGA. Figure 8. Intel ® MCH F C-BGA Package Dimensions (To p and Side View ) pkg_olga_ 593_top -si de U n it s = M illim et e r s 9.
Ballout and Package Information R Intel ® 82845 MCH for SDR Datasheet 135 Figure 9. Intel ® MCH F C-BGA Package Dimensions (Bottom View ) pkg-MCH_olga_593_Bot D E G H K L P R U V Y N W M AA AB AC AD AE AF J F A AH AG AJ 1.270 B C T 10 16 20 35 7 9 11 13 15 17 19 46 1 8 81 2 1 4 22 21 24 23 26 25 28 27 29 1 2 17.
Ballout and Package Information R 136 Intel ® 82845 MCH for SDR Datasheet This page is intentionally left blank..
Testability R Intel ® 82845 MCH for SDR Datasheet 137 8 Testability In the MCH, testability for Autom ated Test Equipment (ATE) board-level testing h as been implem ented as an XOR chain. A n XOR- tree is a chain of XOR gates , each w ith one in put pin connected to it (see Fig ure 10).
Testability R 138 Intel ® 82845 MCH for SDR Datasheet 8.2 XOR Chains Note: RSTIN#, TESTIN#, and all Rc omp bu ff ers are not part of any XOR chain. Table 23.
Testability R Intel ® 82845 MCH for SDR Datasheet 139 Chain 0 Ball Element # Signal Name Note Initial Logic Level M5 31 HA24# I nput 1 K3 32 HA23# Input 1 K4 33 HA17# Input 1 J3 34 HA25# Input 1 L5 3.
Testability R 140 Intel ® 82845 MCH for SDR Datasheet Table 24. XO R Chain 1 Chain 1 Ball Element # Signal Name Note Initial Logic Level N6 1 HADSTDB1# Input 1 H7 2 SCS6# Input 1 G10 3 SCKE2 Input 1 .
Testability R Intel ® 82845 MCH for SDR Datasheet 141 Table 25. XO R Chain 2 Chain 2 Ball Element # Si gnal Name Note Ini ti al Logic Level D10 1 SDQ54 Input 1 C10 2 SDQ21 Input 1 C11 3 SDQ52 Input 1.
Testability R 142 Intel ® 82845 MCH for SDR Datasheet Table 26. XO R Chain 3 Chain 3 Ball El em ent # Signal Nam e Note I nitial Logi c Level G10 1 SCKE0 Input 1 G12 2 SMA12 Input 1 G15 3 SCK4 I nput.
Testability R Intel ® 82845 MCH for SDR Datasheet 143 Chain 3 Ball El em ent # Signal Nam e Note I nitial Logi c Level B25 35 SDQ6 Input 1 C25 36 SDQ38 I nput 1 C27 37 SDQ3 Input 1 D27 38 SDQ35 I npu.
Testability R 144 Intel ® 82845 MCH for SDR Datasheet Chain 4 Ball E l em ent # Signal Name Note Initial Logi c Level N27 20 HI _2 Input 1 M26 21 HI _4 Input 1 N25 22 HI_STB Input 1 L27 23 HI _7 Inpu.
Testability R Intel ® 82845 MCH for SDR Datasheet 145 Chain 5 Ball Element # Signal Name Note Ini tial Logic Level W 24 8 G_TRDY # Input 1 AE23 9 W BF# Input 1 W 23 10 G_STOP # I nput 1 AA23 11 G_C/B.
Testability R 146 Intel ® 82845 MCH for SDR Datasheet Table 29. XO R Chain 6 Chain 6 Ball Element # Si gnal Name Note Initial Logi c Level AC27 1 AD_STB1 Input 1 AF27 2 S B_STB Input 1 AE17 3 CPURST#.
Testability R Intel ® 82845 MCH for SDR Datasheet 147 Chain 6 Ball Element # Si gnal Name Note Initial Logi c Level AC9 35 HD35# Input 1 AD9 36 HD37# Input 1 AH7 37 HD24# Input 1 AH5 38 HD31# Input 1 AG8 39 HD27# I nput 1 Y4 40 DEFE R# I nput 1 W 7 41 RS 1# Input 1 AE24 42 SBA6 Output N/A Table 30.
Testability R 148 Intel ® 82845 MCH for SDR Datasheet Chain 7 Ball E l em ent # SDR Ball name Note I nitial Logi c Level AC3 25 HD13# I nput 1 AB5 26 HD1# Input 1 AC5 27 HD5# Input 1 AA6 28 HD7# Inpu.
Un punto importante, dopo l’acquisto del dispositivo (o anche prima di acquisto) è quello di leggere il manuale. Dobbiamo farlo per diversi motivi semplici:
Se non hai ancora comprato il Intel 845 è un buon momento per familiarizzare con i dati di base del prodotto. Prime consultare le pagine iniziali del manuale d’uso, che si trova al di sopra. Dovresti trovare lì i dati tecnici più importanti del Intel 845 - in questo modo è possibile verificare se l’apparecchio soddisfa le tue esigenze. Esplorando le pagine segenti del manuali d’uso Intel 845 imparerai tutte le caratteristiche del prodotto e le informazioni sul suo funzionamento. Le informazioni sul Intel 845 ti aiuteranno sicuramente a prendere una decisione relativa all’acquisto.
In una situazione in cui hai già il Intel 845, ma non hai ancora letto il manuale d’uso, dovresti farlo per le ragioni sopra descritte. Saprai quindi se hai correttamente usato le funzioni disponibili, e se hai commesso errori che possono ridurre la durata di vita del Intel 845.
Tuttavia, uno dei ruoli più importanti per l’utente svolti dal manuale d’uso è quello di aiutare a risolvere i problemi con il Intel 845. Quasi sempre, ci troverai Troubleshooting, cioè i guasti più frequenti e malfunzionamenti del dispositivo Intel 845 insieme con le istruzioni su come risolverli. Anche se non si riesci a risolvere il problema, il manuale d’uso ti mostrerà il percorso di ulteriori procedimenti – il contatto con il centro servizio clienti o il servizio più vicino.
