Manuale d’uso / di manutenzione del prodotto CY7C1312BV18 del fabbricante Cypress
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18-Mbit QDR™-II SRAM 2-W ord Burst Architecture CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document #: 38-05619 Rev .
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 2 of 29 Logic Block Diagram (CY7C1310BV18) Logic Block Diagram (CY7C1910BV18) 1M x 8 Array CLK A (19:0) Gen. K K Control Logic Address Register D [7:0] Read Add. Decode Read Data Reg.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 3 of 29 Logic Block Diagram (CY7C1312BV18) Logic Block Diagram (CY7C1314BV18) 512K x 18 Array CLK A (18:0) Gen. K K Control Logic Address Register D [17:0] Read Add.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 4 of 29 Pin Configuration The pin configuration for CY7C1310BV18, CY7C1910 BV18, CY7C1312BV18, and CY7 C1314BV18 follow .
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 5 of 29 CY7C1312BV18 (1M x 18) 123456789 10 11 A CQ NC/144M NC/36M WPS BWS 1 K NC/28 8M RPS A NC/72M CQ B NC Q9.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 6 of 29 Pin Definitions Pin Name IO Pin Description D [x:0] Input- Synchronous Data Input Signals. Sampled on the rising edge of K and K clocks during val id write opera tions.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 7 of 29 CQ Echo Clock CQ Referenced with Respect to C . This is a free - running clock and is synchronized to the Input clock for output data (C) of the QDR-II. In the single clock mode , CQ is generated wi th respect to K.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 8 of 29 Functional Overview The CY7C1310BV18, CY7C1910BV18, CY7C1312 BV18, and CY7C1314BV18 are synchronous pipelined Burst SRAMs equipped with a read port and a write p ort.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 9 of 29 Programmable Impedan ce An external resistor , RQ, must be connected between the ZQ pin on the SRAM and V SS to allo w the SRAM to adjust its output driver impedance.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 10 of 29 T ruth T able The truth table for CY7C1310BV18, CY7C1910BV 18, CY7C1312BV18, and CY7C1314BV18 follows. [2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQ Write Cycle: Load address on the rising ed ge of K ; input write data on K and K rising edges.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 1 1 of 29 Write Cycle Descriptions The write cycle description tabl e for CY7C1910BV18 follows. [2, 8] BWS 0 K K Comments L L–H – During the data portion of a write sequence, the single b yte (D [8:0] ) is written into the device.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 12 of 29 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 13 of 29 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister .
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 14 of 29 T AP Controller St ate Diagram The state diagram for the T AP controller follows.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 15 of 29 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 16 of 29 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 17 of 29 Identification R egi ster Definitions Instruction Field Va l u e Description CY7C1310BV18 CY7C1910BV18 CY7 C1312BV18 CY7C1314BV18 Revision Numb er (31:29) 000 000 000 000 V ersion number .
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 18 of 29 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 1 1H 54 7B 81 3G 1.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 19 of 29 Power Up Sequence in QDR-II SRAM QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent unde fined operations. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (all other inputs can be HIGH or LOW).
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 20 of 29 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature ......
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 21 of 29 I SB1 Automatic Power Down Current Max V DD , Both Ports Deselected, V IN ≥ V IH or V IN ≤ V IL f .
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 22 of 29 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Condition s Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 23 of 29 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consor tium Parameter De.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 24 of 29 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 6, 27, 28 ] K 1 2 34 5 8 10 6 7 K RPS W.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 25 of 29 Ordering Information Not all of the speed, package, and temper ature ranges are available. Please cont act your local sale s representative or visit www .
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 26 of 29 167 CY7C1310BV18-167BZC 51-85180 165-Ball Fine Pi tch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1910BV18-167BZC CY7C1312BV18-167BZC CY7C1314BV18-167BZC CY7C1310BV18-167BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 27 of 29 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø 0 . 2 5MCAB Ø0.
CY7C1310BV18, CY7C1910BV18 CY7C1312BV18, CY7C1314BV18 Document #: 38-05619 Rev . *F Page 28 of 29 Document History Page Document Title: CY7C1310BV18/CY7C1910BV18/CY7C1312BV18 /C Y7C1314BV18, 18-Mbit QDR™-II SRAM 2-Word Burst Architecture Document Number: 38-05619 Rev .
Document #: 38-05619 Rev . *F Revised June 2, 2008 Page 29 of 29 QDR RAMs and Qua d Data Ra te RA Ms comprise a ne w fam i ly of pr od uct s developed by Cypress, Hit a chi, IDT , NE C , an d S am s un g. A l l p r oduct and company names mentioned in this d ocume nt a re the tradem arks of their r es pective hold ers.
Un punto importante, dopo l’acquisto del dispositivo (o anche prima di acquisto) è quello di leggere il manuale. Dobbiamo farlo per diversi motivi semplici:
Se non hai ancora comprato il Cypress CY7C1312BV18 è un buon momento per familiarizzare con i dati di base del prodotto. Prime consultare le pagine iniziali del manuale d’uso, che si trova al di sopra. Dovresti trovare lì i dati tecnici più importanti del Cypress CY7C1312BV18 - in questo modo è possibile verificare se l’apparecchio soddisfa le tue esigenze. Esplorando le pagine segenti del manuali d’uso Cypress CY7C1312BV18 imparerai tutte le caratteristiche del prodotto e le informazioni sul suo funzionamento. Le informazioni sul Cypress CY7C1312BV18 ti aiuteranno sicuramente a prendere una decisione relativa all’acquisto.
In una situazione in cui hai già il Cypress CY7C1312BV18, ma non hai ancora letto il manuale d’uso, dovresti farlo per le ragioni sopra descritte. Saprai quindi se hai correttamente usato le funzioni disponibili, e se hai commesso errori che possono ridurre la durata di vita del Cypress CY7C1312BV18.
Tuttavia, uno dei ruoli più importanti per l’utente svolti dal manuale d’uso è quello di aiutare a risolvere i problemi con il Cypress CY7C1312BV18. Quasi sempre, ci troverai Troubleshooting, cioè i guasti più frequenti e malfunzionamenti del dispositivo Cypress CY7C1312BV18 insieme con le istruzioni su come risolverli. Anche se non si riesci a risolvere il problema, il manuale d’uso ti mostrerà il percorso di ulteriori procedimenti – il contatto con il centro servizio clienti o il servizio più vicino.
