Manuale d’uso / di manutenzione del prodotto TCM4300 del fabbricante Texas Instruments
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Data Manual 1996 Mixed-Signal Products.
Printed in U.S.A. 10/96 SL WS010F.
TCM4300 Data Manual Advanced RF Cellular T elephone Interface Circuit (ARCTIC ) SL WS010F October 1996 Printed on Recycled Paper.
IMPORT ANT NOTICE T exas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify , before placing orders, that the information being relied on is current.
iii Contents Section Title Page 1 Introduction 1–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features 1–1 . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv 3.9 TCM4300 to Microcontroller Interface T iming Requirements (Motorola 8-Bit Write Cycle) 3–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 Switching Characteristics, TCM4300 to DSP Interface (Read Cycle) 3–10 .
v List of Illustrations Figure Title Page 3–1 MCLKOUT T iming Diagram 3–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 Microcontroller Interface T iming Requirements (Mitsubishi Configuration Read Cycle, MTS [1:0] = 10) 3–2 .
vi List of T ables T able Title Page 4–1 TCM4300 Receive Channel Control Signals 4–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 RXIP , RXIN, RXQP , and RXQN Inputs (A V DD = 3 V , 4.5 V , 5 V) 4–2 . . . . . . . . . . . .
1–1 1 Introduction T exas Instruments (TI ) TCM4300 IS-54B advanced RF cellular telephone interface circuit (ARCTIC ) provides a baseband interface between the digital signal processor (DSP), the microcontroller , and the RF modulator/demodulator in a dual-mode IS-54B cellular telephone.
1–2 1.2 TCM4300 Functional Block Diagram TXQP TXQN RSSI BA T A/D OUT1 FMRXEN IQRXEN TXEN SCEN SYNOL TXONIND SYNCLK SYNDT A SYNLE [2:0] LCDCONTR D/A TXIP TXIN FM RXQP RXQN A/D RXIP RXIN A/D PWRCONT A.
1–3 1.3 Pin Assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65.
1–4 1.4 T erminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION AFC 11 O Automatic frequency control. The AFC DAC output provides the means to adjust system temperature-compensated reference oscillator (TCXO). AGC 10 O Automatic gain control.
1–5 1.4 T erminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION DSPRW 69 I DSP read/write. A high on DSPR W enables a read operation and a low enables a write operation to the DSP . DSPSTRBL 68 I DSP strobe low . The DSPSTRL (active low) is used in conjunction with DSPCSL to enable read/write operations to the DSP .
1–6 1.4 T erminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION MCDS 48 I Microcontroller data strobe. MCDS is configured by the signals present on MTS0 and MTS1. MCLKIN 64 I Master clock input. The MCLKIN frequency input requirement is 38.
1–7 1.4 T erminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION SCEN 94 O Speech CODEC enable. A high out from SCEN can enable the speech CODEC. SINT 79 O Sample interrupt. SINT is active low . In the analog mode, SINT occurs at 40 kHz; in the digital mode, SINT occurs at 48.
2–1 2 Electrical Specifications This section lists the electrical specifications, the absolute maximum ratings, the recommended operating conditions and operating characteristics for the TCM4300 Advanced RF Cellular T elephone Interface Circuit.
2–2 2.3 Recommended Operating Conditions MIN NOM MAX UNIT Supply voltage, DV DD 3 5.5 V High-level input voltage, V IH Digital 0.7 DV DD DV DD +0.3 V Low-level input voltage, V IL Digital 0 0.3 DV DD V High-level output voltage, V OH Digital 0.7 DV DD DV DD V Low-level output voltage, V OL Digital 0 0.
2–3 2.4.3 T erminal Impedance FUNCTION MIN TYP † MAX UNIT Receive channel input impedance (single ended), RXIP/N and RXQP/N 40 70 k Ω T ransmit channel output impedance (single ended), TXIP/N and TXQP/N 40 50 100 Ω FM input impedance, WBD 25 200 k Ω MCLKOUT impedance MCLKOUT at 3.
2–4 2.4.5 T ransmit I and Q Channel Outputs P ARAMETER MIN TYP MAX UNIT Peak output voltage full scale centered at VCM Differential 2.24 Vp P ea k ou t pu t vo lt age f u ll sca l e, cen t ere d a t VCM Single ended 1.12 V p Nominal output-level (constellation radius) centered Dif ferential 1.
2–5 2.4.7 Auxiliary D /A Converters Slope (AGC, AFC, PWRCONT) AUXFS[1:0] SETTING SLOPE NOMINAL LSB V ALUE (V) NOMINAL OUTPUT VOL T AGE FOR DIGIT AL CODE = 128 (MIDRANGE) (V) NOMINAL OUTPUT VOL T AGE FOR DIGIT AL CODE = 256 † (MAX V ALUE) (V) 00 2.
2–6 2.5 Operating Characteristics Over Full Range of Operating Conditions (Unless Otherwise Noted) 2.5.1 Receive (RX) Channel Frequency Response (RXI, RXQ Input in Digital Mode) P ARAMETER TEST CONDITIONS MIN TYP MAX UNIT F 0.125 V peak-to-peak, 0 kHz to 8 kHz (see Note 4) ± 0.
2–7 2.5.4 T ransmit (TX) Channel Frequency Response (Analog Mode) P ARAMETER TEST CONDITIONS MIN TYP MAX UNIT F 0 kHz to 8 kHz (see Note 4) ± 0.5 dB F 8 kHz to 15 kHz (see Note 4) ± 0.
2–8.
3–1 3 Parameter Measurement Information This section contains the timing waveforms and parameter values for MCLKOUT and several microcontroller interface configurations possible when using the TCM4300. The timing parameters are contained in Section 3.
3–2 3.2 TCM4300 to Microcontroller Interface T iming Requirements (Mitsubishi Read Cycle) (see Figure 3–2 and Note 2) P ARAMETER AL TERNA TE SYMBOL MIN MAX UNIT t su(R/W) Setup time, read/write MC.
3–3 3.3 TCM4300 to Microcontroller Interface T iming Requirements (Mitsubishi Write Cycle) (see Figure 3–3 and Note 2) P ARAMETER AL TERNA TE SYMBOL MIN MAX UNIT t su(R/W) Setup time, read/write M.
3–4 3.4 TCM4300 to Microcontroller Interface T iming Requirements (Intel Read Cycle) (see Figure 3–4 and Note 3) P ARAMETER AL TERNA TE SYMBOL MIN MAX UNIT t su(RA) Setup time, read address MCA st.
3–5 3.5 TCM4300 to Microcontroller Interface T iming Requirements (Intel Write Cycle) (see Figure 3–5 and Note 3) P ARAMETER AL TERNA TE SYMBOL MIN MAX UNIT t su(W A) Setup time, write address MCA.
3–6 3.6 TCM4300 to Microcontroller Interface T iming Requirements (Motorola 16-Bit Read Cycle) (see Figure 3–6 and Note 4) P ARAMETER AL TERNA TE SYMBOL MIN MAX UNIT t su(R/W) Setup time, read/wri.
3–7 3.7 TCM4300 to Microcontroller Interface T iming Requirements (Motorola 16-Bit Write Cycle) (see Figure 3–7 and Note 4) P ARAMETER AL TERNA TE SYMBOL MIN MAX UNIT t su(R/W) Setup time, read/wr.
3–8 3.8 TCM4300 to Microcontroller Interface T iming Requirements (Motorola 8-Bit Read Cycle) (see Figure 3–8 and Note 5) P ARAMETER AL TERNA TE SYMBOL MIN MAX UNIT t su(R/W) Setup time, read/writ.
3–9 3.9 TCM4300 to Microcontroller Interface T iming Requirements (Motorola 8-Bit Write Cycle) (see Figure 3–9 and Note 5) P ARAMETER AL TERNA TE SYMBOL MIN MAX UNIT t su(R/W) Setup time, read/wri.
3–10 3.10 Switching Characteristics, TCM4300 to DSP Interface (Read Cycle) (see Figure 3–10) P ARAMETER AL TERNA TE SYMBOL MIN MAX UNIT t su(R/W) Setup time, read/write DSPR W stable before fallin.
3–1 1 3.1 1 Switching Characteristics, TCM4300 to DSP Interface (Write Cycle) (see Figure 3–1 1) P ARAMETER AL TERNA TE SYMBOL MIN MAX UNIT t su(R/W) Setup time, read/write DSPR W stable before fa.
3–12.
4–1 4 Principles of Operation This section describes the operation of the TCM4300 in detail. NOTE: T iming diagrams and associated tables are contained in Section 3 of this data manual. 4.1 Data T ransfer The interface to both the system digital signal processor and microcontroller is in the form of 2s complement.
4–2 T able 4–2. RXIP , RXIN, RXQP , and RXQN Inputs (A V DD = 3 V , 4.5 V , 5 V) P ARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input voltage range 0.3 AV DD – 0.3 V Input voltage for full- scale Differential 0.5 Vp-p Input voltage for full scale digital output Single ended 0.
4–3 T able 4–3. Receive (RX) Channel Frequency Response (FM Input in Analog Mode) P ARAMETER TEST CONDITIONS MIN TYP MAX UNIT F 25V k k 0 kHz to 6 kHz (see Note 1) ± 0.5 dB Frequency response 2.5 V peak-to-peak 20 kHz to 30 kHz (see Note 2) –1 8 dB qy p pp 34 kHz to 46 kHz (see Note 3) –4 8 Peak-to-peak group delay distortion 2.
4–4 square-root raised-cosine (SQRC) shaping filter with a roll-off rate of α = 0.35 and converted to sampled analog form by two 9-bit digital-to-analog converters (DACs). The output of the DAC is then filtered by a continuous-time resistance-capacitance (RC) filter .
4–5 T able 4–6. T ransmit (TX) Channel Frequency Response (Digital Mode) P ARAMETER TEST CONDITIONS MIN TYP MAX UNIT F 0 kHz to 8 kHz (see Note 4) ± 0.
4–6 delay after the last symbol occurs (2 SINT periods before TXGO goes low); then the transmit outputs decay to zero differential voltage (each output at the voltage supplied to the VCM input terminal). The shape of the decay is the transient resulting from the internal SQRC filtering.
4–7 DQ CLK Dibit In TXGO DQ CLK SINT BST Offset Delay Channel Delay (15.5 SINT Periods) TXI, TXQ BST Offset Delay P AEN Delay P AEN Delay = 0, 1/4, 1/2, 3/4 Transmit Channel Delay + d(T/8) Occurs from last symbol (2 SINT periods) before TXGO goes low P AEN Delay + d(T/8) TXGO high: 9.
4–8 T able 4–8. T ypical Bit-Error-Rate Performance (WBD_BW = 000) P ARAMETER TEST CONDITIONS MIN MAX UNIT P ARAMETER MEAN CNR MIN MAX UNIT Bi –5 0.4 dB Bi 0 0.279 dB Bi 5 0.143 dB Bit error rate 10 0.056 dB 15 0.0192 20 0.00623 25 0.00199 The WBDD is controlled by the bits in the control register WBDCtrl (see T able 4–9).
4–9 At the same time, the interrupts DWBDINT and MWBDFINT are asserted. The interrupt rate is 800 µ s (8 bits/10 kHz). These interrupts are individually cleared when the WBD register is read by the corresponding processor . They can also be cleared by their respective processor by writing a 1 to the corresponding clear WBD bit.
4–10 4.9 Auxiliary DACs, LCD Contrast Converter Auxiliary DACs generate AFC, AGC and power control signals for the RF system. These three D/A converters are updated when the corresponding data is received from the DSP .
4–1 1 4.9 Auxiliary DACs, LCD Contrast Converter (continued) T able 4–12. Auxiliary D /A Converters Slope (LCDCONTR) AUXFS[1:0] SETTING SLOPE NOMINAL LSB V ALUE (V) NOMINAL OUTPUT VOL T- AGE FOR DIGIT AL CODE = 8 (MIDRANGE) (V) NOMINAL OUTPUT VOL T AGE FOR DIGIT AL CODE = 16† (MAX V ALUE) (V) 00 2.
4–12 CMCLK CSCLK Codec Master Clock 2.048 MHz Codec Sample Clock 8 kHz Figure 4–4. Codec Master and Sample Clock Timing 4.1 1.1 Clock Generation There are three options for generating the master clock. A fundamental crystal or a third-overtone crystal with a frequency of 38.
4–13 4.1 1.5 Phase-Adjustment Strategy For an IS-54 system in the digital mode, receiver sample timing must be phase adjusted to synchronize the A/D conversions to optimum sampling points of the received symbols, and to synchronize the mobile unit timing to the base station timing.
4–14 ÷ 17, 18, 19, 20 Adjust Counter B = 0 ÷ 256 Bits 0 – 5 RCO Adjust Counter A ÷ 3, 4, 5 Phase-Adjusted 9.72-MHz Clock ÷ 243/ ÷ 200 Clock Divider Chain Analog/Digital Mode (MODE bit) Frequency Synth. Clock 303.75 kHz WBD Demod. 6.48 MHz ADC Clocks DAC Clocks ÷ N 5 10 N = (2, 3, .
4–15 4.12 Frequency Synthesizer Interface The synthesizer interface provides a means of programming three synthesizers. The synthesizer-side outputs are a data line, a clock line, and three latch enable lines that separately strobe data into each synthesizer .
4–16 D E D E D E SEL 0 SEL 1 SEL 2 S R A B A A = B A = B B A B ≤ A B Clock Circuit HIGHV AL DMUX LOWV AL NUMCLKS 5 BIT CNT [0 . . . 31] M U X 32 32-Bit Data Register 8 Control Registers 5 5 5 3 Re.
4–17 The SynData0 register contains the least significant bits of the 32-bit data register . SynData3 contains the most significant bits. The bits in the SynCtrl0, SynCtrl1, and SynCtrl2 registers are allocated as shown in Figure 4–7.
4–18 Up to 31 data bits plus a latch enable (SYNLE0,1,2) can be programmed in one programming cycle. When data greater than or equal to 32 bits must be programmed, TI recommends using two or more programming cycles with data in each cycle and a latch enable in the final programming cycle.
4–19 In addition to allowing control of power to external functional modules, these power control bits combined with other control bits are used to control internal TCM4300 functions.
4–20 In the analog mode, (MODE bit set low), P AEN is high whenever TXEN is active and SYNOL is low . The SYNOL input can be used as an indication to the TCM4300 that the external synthesizers are out of lock. The P AEN signal is gated by SYNOL to prevent of f-channel transmissions.
4–21 4.15 Microcontroller Register Map The microcontroller can access 17 locations within the TCM4300. The register locations are 8 bits wide as shown in T able 4–16 and T able 4–17.
4–22 T able 4–17. Microcontroller Register Definitions ADDR NAME CA TEGORY R/W 00h WBDCtrl Wide-band data W 00h WBD Wid e- b an d d a t a R 01h FIFO FIFO A(B) microcontroller to DSP (DSP to microc.
4–23 T able 4–18. WBDCtrl Register BIT R/W NAME FUNCTION RESET V ALUE 9 R/W WBD_LCKD Wide-band data lock data. WBD_LCKD determines whether edge detector is locked (1) or unlocked (0). 0 8 R/W WBD_ON Wide-band data on. WBD_ON turns the WBDD module on/of f (1/0).
4–24 T able 4–19. MStatCtrl Register Bits BIT R/W NAME FUNCTION RESET V ALUE 7 R SYNOL Synthesizer out of lock. SYNOL is equal to the level applied to SYNOL input pin. SYNOL can be used as an input for an externally generated status signal to prevent transmission when external synthesizers are out of lock.
4–25 4.19 DSP Register Map The register map accessible to the DSP port is shown in T able 4–20 and T able 4–21. There are 14 system addressable locations. Note that the write address of FIFO B is the same as the read address of FIFO A. Figure 4-1 1 details the connection of TCM4300 to an example DSP .
4–26 D[15:6] A[3:0] IS R/W STRB INT 1 INT 3 INT 4 DSPD[9:0] DSP A[3:0] DSPCSL DSPRW DSPSTRBL SINT CINT BDINT DSP TCM4300 10 4 Figure 4–1 1. DSP Interface 4.20 Wide-Band Data Registers Bit 9 of the wide-band data register is the most recently received bit as shown below .
4–27 4.22 DSP Status and Control Registers DIntCtrl, Clear and Send Bits: The bit names in the DIntCtrl register indicate the action to be taken when a 1 is written to the respective bit. When these bits are being read, a 1 indicates that the corresponding interrupt is pending.
4–28 4.23 Reset A low on RSINL causes the TCM4300 internal registers to assume their reset values. The power-on reset circuit also causes internal reset. However , the logic level at RSINL has no effect on reset outputs RSOUTH and RSOUTL. The effects of resetting the TCM4300 are described in the following paragraphs.
4–29 4.24 Microcontroller Interface The microcontroller interface of the TCM4300 is a general purpose bus interface (see T able 4–24) which ensures compatibility with a wide range of microcontrollers, including the Mitsubshi M37700 series and most Intel and Motorola series.
4–30 4.24.2 Mitsubishi Microcontroller Mode of Operation When the microcontroller type select MTS1 and MTS0 inputs are held high and low , respectively , the TCM4300 microcontroller interface is configured in Mitsubishi mode.
4–31 T able 4–28. Microcontroller Interface Connections for Motorola Mode (16 bits) TCM4300 TERMINAL MICROCONTROLLER TERMINAL MTS1, MTS0 T ie to logic levels: high and low , respectively MCCSH Not.
4–32.
5–1 5 Mechanical Data 5.1 PZ (S-PQFP-G100) PLASTIC QUAD FLA TP ACK 4040149 / A 03/95 50 26 0,13 NOM Gage Plane 0,25 0,45 0,75 0,05 MIN 0,27 51 25 75 1 12,00 TYP 0,17 76 100 SQ SQ 15,80 16,20 13,80 1,35 1,45 1,60 MAX 14,20 0 ° – 7 ° Seating Plane 0,08 0,50 M 0,08 NOTES: A.
IMPORT ANT NOTICE T exas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify , before placing orders, that the information being relied on is current.
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