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TMS3320C5515 DSP System User's Guide Literature Number: SPRUFX5A October 2010 – Revised November 2010.
2 SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated.
Contents Preface ....................................................................................................................................... 9 1 System Control ...............................................................................
www.ti.com List of Figures 1-1. Functional Block Diagram ................................................................................................ 13 1-2. DSP Memory Map ..........................................................................
www.ti.com 1-48. EMIF System Control Register (ESCR) [1C33h] ...................................................................... 76 1-49. EMIF Clock Divider Register (ECDR) [1C26h] ...................................................................
www.ti.com List of Tables 1-1. ............................................................................................................................... 14 1-2. DARAM Blocks .......................................................................
www.ti.com 1-48. Output Slew Rate Control Register (OSRCR) Field Descriptions ................................................... 66 1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions ....................................................
8 List of Tables SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated.
Preface SPRUFX5A – October 2010 – Revised November 2010 Read This First About This Manual This document describes various aspects of the TMS320C5515 digital signal processor (DSP) including: system memory, device clocking options and operation of the DSP clock generator, power management features, interrupts, and system control.
Related Documentation From Texas Instruments www.ti.com SPRUFO4 — TMS320C5515/14/05/04/VC05/VC04 Digital Signal Processor (DSP) General-Purpose Input/Output (GPIO) User's Guide. This document describes the general-purpose input/output (GPIO) on the TMS320C5515/14/05/04/VC05/VC04 digital signal processor (DSP) devices.
www.ti.com Related Documentation From Texas Instruments SPRUGH5 — TMS320C5505 DSP System User's Guide. This document describes various aspects of the TMS320C5505 digital signal processor (DSP) including: system memory, device clocking options and operation of the DSP clock generator, power management features, interrupts, and system control.
12 Read This First SPRUFX5A – October 2010 – Revised November 2010 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated.
PLL/Clock Generator Power Management Pin Multiplexing JT AG Interface 64 KB DARAM 256 KB SARAM 128 KB ROM Switched Central Resource (SCR) Input Clock(s) FFT Hardware Accelerator C55x™ DSP CPU DSP System LCD Bridge Display I S (x4) 2 I C 2 SPI UART Serial Interfaces 10-Bit SAR ADC App-Spec USB 2.
Introduction www.ti.com 1.1.2 CPU Core The C55x CPU is responsible for performing the digital signal processing tasks required by the application. In addition, the CPU acts as the overall system contr.
www.ti.com Introduction Note that for the FFT routines, output data is dependent on the return value (T0). If return = 0 output data is in-place, meaning the result will overwrite the input buffer. If return =1, output data is placed in the scratch buffer.
System Memory www.ti.com modes. • Three 32-bit timers with 16-bit prescaler; one timer supports watchdog functionality. • A USB 2.0 slave. • A 10-bit successive approximation (SAR) analog-to-digital converter with touchscreen conversion capability.
0001 0000h 64K Minus 192 Bytes DARAM (D) 0009 0000h SARAM 256K Bytes External-CS2 Space (C) 0200 0000h 0300 0000h 0400 0000h 0500 0000h 050E 0000h 128K Bytes Asynchronous (if MPNMC=1) 128K Bytes ROM (.
System Memory www.ti.com Table 1-2. DARAM Blocks (continued) Memory Block CPU Byte Address Range DMA/USB Controller Byte Address Range DARAM 6 00 C000h - 00 DFFFh 0001 C000h - 0001 DFFFh DARAM 7 00 E000h - 00 FFFFh 0001 E000h - 0001 FFFFh 1.
www.ti.com System Memory 1.2.1.3 On-Chip Single-Access Read-Only Memory (SAROM) The zero-wait-state ROM is located at the CPU byte address range FE 0000h - FF FFFFh. The ROM is composed of four 16K-word blocks, for a total of 128K-bytes of ROM. Each ROM block can perform one access per cycle (one read or one write).
Device Clocking www.ti.com pins for the load mode register command. During the mobile SDRAM initialization, the device issues the load mode register initialization command to two different addresses that differ in only the BA0 and BA1 address bits. These registers are the Extended Mode register and the Mode register.
www.ti.com Device Clocking RTC_XO pins. RTC core (CV DDRTC ) must be powered all the time but the 32.768-KHz crystal can be disabled if CLKIN is used as the clock source for the DSP. However, when the RTC oscillator is disabled, the RTC peripheral will not operate and the RTC registers (I/O address range 1900h - 197Fh) will not be accessible.
CLKSEL 1 0 CLKIN PCGCR1 [SYSCLKDIS] LS 1 0 LS CCR2 [SYSCLKSEL] SYSCLK System Clock Generator ST3_55[CLKOFF] CLKOUT ICR[HW AI] FFT Hardware ICR[MPORTI] MPORT Clock ICR[XPORTI] XPORT Clock PCGCR2[DMA1CG.
www.ti.com System Clock Generator 1.3.2 Clock Domains The device has many clock domains defined by individually disabled portions of the clock tree structure. Understanding the clock domains and their clock enable/disable control registers is very important for managing power and for ensuring clocks are enabled for domains that are needed.
CLKREF Reference Divider 1 0 CGCR2[RDBYP ASS] PLL LS PLLIN PLLOUT Output Divider 0 CGCR4. [OUTDIVEN] 1 0 CCR2. [SYSCLKSEL] LS SYSCLK CLKSEL 1 0 CLKIN RTC Clock LS RTC OSC RTC_XI RTC_XO 32.
www.ti.com System Clock Generator When the PLL is powered up (PLL_PWRDN = 0), the PLL will start its phase-locking sequence. You must keep the clock generator in BYPASS MODE for at least 4 mS while the phase-locking sequence is ongoing. See Section 1.
System Clock Generator www.ti.com 1.4.2.4 DSP Reset Conditions of the System Clock Generator The following sections describe the operation of the system clock generator when the DSP is held in reset state and the DSP is removed from its reset state. 1.
www.ti.com System Clock Generator 1.4.3.1.2 Register Bits Used in the BYPASS MODE Table 1-7 describes the bits of the clock generator control registers that are used in the BYPASS MODE. For detailed descriptions of these bits, see Section 1.4.4 . Table 1-7.
System Clock Generator www.ti.com Table 1-9. Clock Generator Control Register Bits Used In PLL Mode (continued) Register Bit Role in Bypass Mode RDRATIO Specifies the divider ratio of the reference divider. M Specify the multiplier value for the PLL. OUTDIVEN Determines whether the output divider is bypassed.
www.ti.com System Clock Generator Table 1-11 shows programming examples for different PLL MODE frequencies. Table 1-11. Examples of Selecting a PLL MODE Frequency, When CLK_SEL=L RDBYPASS OUTDIVEN M RDRATIO ODRATIO PLL Output Frequency 1 0 173h X X 32.
System Clock Generator www.ti.com 1.4.4.1 Clock Generator Control Register 1 (CGCR1) [1C20h] The clock generator control register 1 (CGCR1) is shown in Figure 1-6 and described in Table 1-13 .
www.ti.com System Clock Generator 1.4.4.3 Clock Generator Control Register 3 (CGCR3) [1C22h] The clock generator control register 3 (CGCR3) is shown in Figure 1-8 and described in Table 1-15 . Figure 1-8. Clock Generator Control Register 3 (CGCR3) [1C22h] 15 0 INIT R/W-0806h LEGEND: R/W = Read/Write; - n = value after reset Table 1-15.
System Clock Generator www.ti.com 1.4.4.5 Clock Configuration Register 1 (CCR1) [1C1Eh] The clock configuration register 1 (CCR1) is shown in Figure 1-10 and described in Table 1-17 . Figure 1-10. Clock Configuration Register 1 (CCR1) [1C1Eh] 15 1 0 Reserved SDCLK_EN R-0 R/W-0 LEGEND: R = Read only; - n = value after reset Table 1-17.
www.ti.com Power Management 1.5 Power Management 1.5.1 Overview In many applications there may be specific requirements to minimize power consumption for both power supply (and battery) and thermal considerations. There are two components to power consumption: active power and leakage power.
Power Management www.ti.com Table 1-20. DSP Power Domains Power Domains Description Real-Time Clock Power Domain This domain powers the real-time clock digital circuits and oscillator pins ( RTC_XI, (CV DDRTC ) RTC_XO). Nominal supply voltage can be 1.
www.ti.com Power Management There are two distinct methods of clock gating. The first uses the ICR CPU register and the CPU's IDLE instruction. This method is used for the following domains: CPU, IPORT, DPORT, MPORT, XPORT & HWA. See Figure 1-3 for a diagram of these domains.
Power Management www.ti.com 1.5.3.1.1 Idle Configuration Register (ICR) [0001h] and IDLE Status Register (ISTR) [0002h] Table 1-21 describes the read/write bits of ICR, and Table 1-22 describes the read-only bits of ISTR.
www.ti.com Power Management Figure 1-13. Idle Status Register (ISTR) [0002h] 15 10 9 8 Reserved HWAIS IPORTIS R-0 R-0 R-0 7654 10 MPORTIS XPORTIS DPORTIS Reserved CPUIS R-0 R-0 R-0 R-0 R-0 LEGEND: R = Read only; - n = value after reset Table 1-22. Idle Status Register (ISTR) Field Descriptions Bit Field Value Description 15-10 Reserved 0 Reserved.
Power Management www.ti.com Table 1-23. CPU Clock Domain Idle Requirements (continued) To Idle the Following Module/Port Requirements Before Going to Idle XPORT CPU CPUI must also be set. DPORT 1.5.3.1.3 Clock Configuration Process The clock configuration indicates which portions of the CPU clock domain will be idle, and which will be active.
www.ti.com Power Management 1.5.3.2.1 Peripheral Clock Gating Configuration Registers (PCGCR1 and PCGCR2) [1C02 - 1C03h] The peripheral clock gating configuration registers (PCGRC1 and PCGCR2) are used to disable the clocks of the DSP peripherals.
Power Management www.ti.com Table 1-24. Peripheral Clock Gating Configuration Register 1 (PCGCR1) Field Descriptions (continued) Bit Field Value Description 6 I2CCG I2C clock gate control bit. This bit is used to enable and disable the I2C peripheral clock.
www.ti.com Power Management The peripheral clock gating configuration register 2 (PCGCR2) is shown in Figure 1-15 and described in Table 1-25 . Figure 1-15.
Power Management www.ti.com 1.5.3.2.2 Peripheral Clock Stop Request/Acknowledge Register (CLKSTOP) [1C3Ah] You must execute a handshaking procedure before stopping the clock to the EMIF, USB, and UART. This handshake procedure ensures that current bus transactions are completed before the clock is stopped.
www.ti.com Power Management Table 1-26. Peripheral Clock Stop Request/Acknowledge Register (CLKSTOP) Field Descriptions (continued) Bit Field Value Description 1 EMFCLKSTPACK EMIF clock stop acknowledge bit. This bit is set to 1 when the EMIF has acknowledged a request for its clock to be stopped.
Power Management www.ti.com 1.5.3.4.1 Clock Configuration Process The clock configuration process for the USB clock domain consists of disabling the USB peripheral clock followed by disabling the USB on-chip oscillator. This procedure will completely shut off USB module, which does not comply with USB suspend/resume protocol.
www.ti.com Power Management Table 1-27. USB System Control Register (USBSCR) Field Descriptions (continued) Bit Field Value Description 13 USBVBUSDET USB VBUS detect enable. The USB VBUS pin has two comparators that monitor the voltage level on the pin.
Power Management www.ti.com 1.5.4 Static Power Management 1.5.4.1 RTC Power Management Register (RTCPMGT) [1930h] This register enables static power management with power down and wake up register bits as described in the device-specific data sheet and, more generally, below.
www.ti.com Power Management 1.5.4.2 RTC Interrupt Flag Register (RTCINTFL) [1920h] The RTC interrupt flag register (RTCINTFL) is shown in Figure 1-19 and described in Table 1-29 .
Power Management www.ti.com 1.5.4.3 Internal Memory Low Power Modes To save power, software can place on-chip memory (DARAM or SARAM) in one of two power modes: memory retention mode and active mode. These power modes are activated through the SLPZVDD and SLPZVSS bits of the RAM Sleep Mode Control Register 1-5 (RAMSLPMDCNTLR[1:5]) .
www.ti.com Power Management Figure 1-21. RAM Sleep Mode Control Register2 [0x1C2A] 15 14 13 12 11 10 9 8 SARAM7 SARAM7 SARAM6 SARAM6 SARAM5 SARAM5 SARAM4 SARAM4 SLPZVDD SLPZVSS SLPZVDD SLPZVSS SLPZVDD.
Power Management www.ti.com 1.5.5 Power Configurations The power-saving features described in the previous sections, such as peripheral clock gating, and on-chip memory power down to name a few, can be combined to form a power configuration.
www.ti.com Power Management 1.5.5.1 IDLE2 Procedure In this power configuration all the power domains are turned on, the RTC and clock generator domains are enabled, the CPU domain is disabled, and the DSP peripherals are disabled. When you enter this power configuration all CPU and peripheral activity in the DSP is stopped.
Power Management www.ti.com 1.5.5.2 IDLE3 Procedure In this power configuration all the power domains are turned on, the CPU and clock generator domains are disabled, and the RTC clock domain is enabled. The DSP peripherals and the USB are also disabled in this mode.
www.ti.com Interrupts When the core voltage is increased (1.05 V to 1.3 V) clock speed is not an issue since the device can operate faster at the higher voltage. However, when switching from 1.05 V to 1.3 V software must allow time for the voltage transition to reach the 1.
Interrupts www.ti.com Table 1-32. Interrupt Table (continued) SOFTWARE RELATIVE NAME (TRAP) LOCATION PRIORITY FUNCTION EQUIVALENT (HEX BYTES) (1) - SINT28 0xE0 15 Software interrupt #28 - SINT29 0xE8 16 Software interrupt #29 - SINT30 0xF0 17 Software interrupt #30 - SINT31 0xF8 18 Software interrupt #31 1.
www.ti.com Interrupts The interrupt flag register (IFR1) and interrupt enable register 1 (IER1) bit layouts are shown in Figure 1-26 and described in Table 1-34 .
Interrupts www.ti.com 1.6.3 Timer Interrupt Aggregation Flag Register (TIAFR) [1C14h] The CPU has only one interrupt flag that is shared among the three timers. The CPU's interrupt flag is bit 4 (TINT) of the IFR0 & IER0 registers (see Figure 1-25).
www.ti.com System Configuration and Control 1.7 System Configuration and Control 1.7.1 Overview The DSP includes system-level registers for controlling, configuring, and reading status of the device.
System Configuration and Control www.ti.com 1.7.2.1 Die ID Register 0 (DIEIDR0) [1C40h] The die ID register 0 (DIEIDR0) is shown in Figure 1-27 and described in Table 1-36 . Figure 1-27. Die ID Register 0 (DIEIDR0) [1C40h] 15 0 DIEID0 R LEGEND: R = Read only; - n = value after reset Table 1-36.
www.ti.com System Configuration and Control 1.7.2.4 Die ID Register 3 (DIEIDR3[15:0]) [1C43h] The die ID register 3 (DIEIDR3) is shown in Figure 1-30 and described in Table 1-39 . Figure 1-30. Die ID Register 3 (DIEIDR3[15:0]) [1C43h] 15 12 11 0 DesignRev DIEID3 R R LEGEND: R = Read only; - n = value after reset Table 1-39.
System Configuration and Control www.ti.com 1.7.2.7 Die ID Register 6 (DIEIDR6) [1C46h] The die ID register 6 (DIEIDR6) is shown in Figure 1-33 and described in Table 1-42 . Figure 1-33. Die ID Register 6 (DIEIDR6) [1C46h] 15 0 Reserved R LEGEND: R = Read only; - n = value after reset Table 1-42.
www.ti.com System Configuration and Control 1.7.3 Device Configuration The DSP includes registers for configuring pin multiplexing, the pin output slew rate, the internal pull-ups and pull-downs, DSP_LDO voltage selection and USB_LDO enable.
System Configuration and Control www.ti.com Table 1-44. EBSR Register Bit Descriptions Field Descriptions Bit Field Value Description 15 Reserved 0 Reserved.
www.ti.com System Configuration and Control Table 1-44. EBSR Register Bit Descriptions Field Descriptions (continued) Bit Field Value Description 2 A17_MODE A17 Pin Mode Bit. This bit controls the pin multiplexing of the EMIF address 17 (EM_A[17]) and general-purpose input/output pin 23 (GP[23]) pin functions.
System Configuration and Control www.ti.com Table 1-45. RTCPMGT Register Bit Descriptions Field Descriptions Bit Field Value Description 15-5 Reserved 0 Reserved. Read-only, writes have no effect. 4 WU_DOUT Wakeup output, active low/open-drain. 0 WAKEUP pin driven low.
www.ti.com System Configuration and Control Figure 1-37. LDO Control Register (LDOCNTL) [7004h] 15 8 Reserved R-0 7 2 1 0 Reserved DSP_LDO_V USB_LDO_EN R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 1-46.
System Configuration and Control www.ti.com 1.7.3.4 Output Slew Rate Control Register (OSRCR) [1C16h] To provide the lowest power consumption setting, the DSP has configurable slew rate control on the EMIF and CLKOUT output pins.
www.ti.com System Configuration and Control 1.7.3.5 Pull-Up/Pull-Down Inhibit Register (PDINHIBR1, PDINHIBR2, and PDINHIBR3 [1C17h, 1C18h, and 1C19h] The device allows you to individually enable or disable the internal pull-up and pull-down resistors.
System Configuration and Control www.ti.com Table 1-49. Pull-Down Inhibit Register 1 (PDINHIBR1) Field Descriptions (continued) Bit Field Value Description 2 S02PD Serial port 0 pin 2 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.
www.ti.com System Configuration and Control Table 1-50. Pull-Down Inhibit Register 2 (PDINHIBR2) Field Descriptions (continued) Bit Field Value Description 5 A20PD EMIF A[20] pin pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.
System Configuration and Control www.ti.com Table 1-51. Pull-Down Inhibit Register 3 (PDINHIBR3) Field Descriptions (continued) Bit Field Value Description 10 PD10PD Parallel port pin 10 pull-down inhibit bit. Setting this bit to 1 disables the pin's internal pull-down.
www.ti.com System Configuration and Control 1.7.4.1 DMA Synchronization Events The DMA controllers allow activity in their channels to be synchronized to selected events. The DSP supports 20 separate synchronization events and each channel can be tied to separate sync events independent of the other channels.
System Configuration and Control www.ti.com 1.7.4.2.1 DMA Interrupt Flag Register (DMAIFR) [1C30h] and DMA Interrupt Enable Register (DMAIER) [1C31h] The DSP includes two registers for aggregating the four channel interrupts of the four DMA controllers.
www.ti.com System Configuration and Control 1.7.4.2.2 DMAn Channel Event Source Registers (DMAnCESR1 and DMAnCESR2) [1C1Ah, 1C1Bh, 1C1Ch, 1C1Dh, 1C36h, 1C37h, 1C38h, and 1C39h] When SYNCMODE = 1 in a .
System Configuration and Control www.ti.com To reset a peripheral or group of peripherals, follow these steps: 1. Set COUNT = 08h in PSRCR. 2. Initiate the desired peripheral reset by setting to 1 the bits of PRCR. 3. Do not attempt to access the peripheral for at least the number of clock cycles set in the PSRCR register.
www.ti.com System Configuration and Control Table 1-59. Peripheral Reset Control Register (PRCR) Field Descriptions (continued) Bit Field Value Description 5 PG3_RST Peripheral group 3 software reset bit. Drives the MMC/SD0, MMC/SD1, I2S0, and I2S1 reset signal.
System Configuration and Control www.ti.com Table 1-60. Effect of BYTEMODE Bits on EMIF Accesses BYTEMODE Setting CPU Access to EMIF Register CPU Access To External Memory BYTEMODE = 00b (16-bit Entir.
www.ti.com System Configuration and Control 1.7.7 EMIF Clock Divider Register (ECDR) [1C26h] The EMIF clock divider register (ECDR) controls the input clock frequency to the EMIF module. When EDIV = 1 (default), the EMIF operates at the same clock rate as the system clock (SYSCLK).
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