Manuale d’uso / di manutenzione del prodotto 41210 del fabbricante Intel
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Intel® 41210 Serial to Parallel PCI Bridge Design Guid e May 2005 Order Num ber: 27880 1-004.
ii Intel® 41 210 Serial to Parallel PCI Bri dge Design G uide INFORMA TION IN THIS DOCUM ENT IS PROVIDE D IN CONNECTION WIT H INTEL ® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTO PPEL OR OTHERWISE, T O ANY INTELLECTUAL PROPERTY RIG H TS IS GRANTED BY THIS DOCUMENT .
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide iii Contents Contents 1 About This Document ................... ............. ................... ............. ................... ............. ................... 7 1.1 Terminology and Defin itions .
iv Intel® 41 210 Serial to Parallel PCI Bri dge Design G uide Contents 8.6.1 Embedde d PCI-X 133 MHz ..... ............. ................... ............. ................... ............. . 39 8.6.2 Embedde d PCI-X 100 MHz ..... ............. ......
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide v Contents 22 PCI 33 MHz Embedded M ode Rou ting Topolo gy ......... ............. ................... ............. ................. 4 3 23 PCI Ana log Voltage Fi lter Circui t ............
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Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 7 About This Document 1 Thi s d ocu m ent provi des l a you t inf orma tion a nd gu idel ines for de sign ing p latf orm o r add- in bo ard applications with the Intel ® 41210 Serial to Paralle l PCI Bri dge (also c alled the 41210 Bridge).
8 Intel® 41 210 Serial to Parallel PCI Bri dge Design G uide About This Document PCB Printed circuit board. Example manufacturing process consists of the following steps: • Consists of alt ernating layers of core and prepreg stacked • The finished PCB is heated and cured.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 9 Introduction 2 The Intel ® 41210 Serial to Parallel PCI Bridge integrates tw o PCI Exp ress-to -PCI bridges. Each bridge f ollows the P CI-to-PCI Bridge progr amming mod el. The PCI Ex press por t is complia nt to the PCI Expr ess Specification , Revision 1.
10 Intel® 41 210 Serial to Parallel PCI Bri dge Design G uide Introduction • T unable i nbound read prefetch algo rithm for PCI MRM/MRL commands • Local initialization v ia SMBu s • Secondary side initializat ion via T ype 0 configuration cycles.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 11 Introduction 2.4.2 Micro control ler Connections to the 41210 Bridge The following diagr am shows the SMB interface f r om the 4121 0 Bridge to the micr ocontroller .
12 Intel® 41 210 Serial to Parallel PCI Bri dge Design G uide Introduction 2.5 JT AG • Compliant with IEEE S tandar d T est Access Port and Bo undary Sca n Ar chitectur e 1 149.1a 2.6 Related Documents • Intel® 41210 Serial to Parallel PCI Bridge Design Specifi cati on (EDS) , Revision 1.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 13 Introduction 2.7 Int el ® 41210 Serial to Parallel PCI Bridge Applications This sectio n provide s a block di agram for a t ypical the 41 210 Bridge application. This app lication shows a PCI-E adapter card with two Dual 2Gb Fi bre Channel controllers.
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Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 15 Package Information 3 3.1 Package Specification The 41210 B ridge is in a 567-b all FCBGA p ackage, 31m m X 31mm in size, with a 1.27mm ball pitch. Figure 5. T op View - 41210 Bri dge 567-B all FCBGA Pac kage Dimen sions Pkg_567- Bal l _Top 0.
16 Intel® 41 210 Serial to Parallel PCI Bri dge Design G uide Package Information Figure 6. B ottom V iew - 41210 Bridge 567-Ball FCBGA Package Dimensions B2711-01 31.00 – 0.100 31.00 – 0.100 29.2100 8X 14.605 23X 1.270 23X 1.270 4X 15.500 4X 0.635 (0.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 17 Package Informatio n Figure 7. Side View - 4121 0 Bridge 5 67-Ball FCBG A Package Dim ensions B2712-01 1.170 – 0.085 H 1.940 – 0.150 J Die FC BGA Substrate 0.100 – 0.025 Die Solder Bumps Underfill Epoxy 0.
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Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 19 Power Plane Layout 4 This chapter provides deta ils on the decoupl ing and volt age planes needed t o bias the 4121 0 Bridge package. 4.1 41210 Bridge Deco upling Guidelin es Ta b l e 2 li sts the decoupling guidelines for the 412 10 Brid ge.
20 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Power P lane Layout Figure 9 . D ecoupling Placement for PCI/P CI-X 1.5V an d 3.3V V oltage Planes B2714-01 Capacitor Legend 0603-0.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 21 Power Plan e La yout T abl e 2. 41210 Bri dge Decoup ling Guidel ines 4.2 S plit V olt age Planes There are two 1.5V v oltage pl anes that supp ly power to th e 41210 Bridge: • VCC15:1 .
22 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Power P lane Layout Note: Linear volt age regulator s are reco mmended when us ing 1.5 V olt power supplie s.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 23 41210 Bridge Reset and Power Timing Considerations 5 This chapter describes the 41210 Bridge reset tim in g considerations.
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Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 25 General Routing Guidelines 6 This chapter pr ovides some basi c routing gu idelines for layou t and design of a print ed circuit board using th e 41210 Br idge. The high-s peed clockin g required when designing w ith the 4121 0 Bridge requires special attention to si gnal integrity .
26 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide General Routing Guidelines • A void slots in the gro und plane. S lots increas es mutual inductance th us increas ing crosstalk. • Make sure th at ground pl ane surro unding connect or pin fields are n ot completely cleared out.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 27 General Routing Guidelines 6.4 Power Distribution and Decoup ling Have ample deco upling to g round, for the power p l anes, to minimize the ef fects of the switching currents. Thr ee types of decoupling are: th e bulk, the high- frequency ceramic, and th e inter-plan e capacitors.
28 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide General Routing Guidelines Note: Using stripline transmiss ion lines may give better results than microst rip.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 29 Board Layout Guidelines 7 This chapter pr ovides details on adap ter card stack up suggestions.
30 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Board Layout Guide lines NOT E: Each interface will set the trace spacing bas ed on its signal integrity of differential impedance requirements. For the pur poses of the building the trans mission line m odels, it is assumed the art work is very accurate and therefore a constant.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 31 PCI-X Layout Guidelines 8 This chapt er describes s everal factors to be consid ered with a 412 10 Brid ge PCI/PCI-X des ign. These include the PCI IDSEL, PC I RCOMP , PCI Interrupts and PCI arbitration.
32 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI-X Layo ut Guidelines Note: PCI Express A ssert_IN Tx/Deassert _INTx messag es are not i nhibited by the BME bi t.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 33 PCI-X Layout Guidelines • Priority group for a master (i.e., whether a master is in low priority group o r high priority grou p).
34 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI-X Layo ut Guidelines T able 7. PCI/PCI-X Frequency/Mode Stra ps Note: All signals s ampled on the rising ed ge of PERST # .
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 35 PCI-X Layout Guidelines B_CBE#[7 :4], B_DEVSEL#, B_FRA ME#, B_INT A#, B_INT B#, B_IN TC#, B_IN TD#, B_IRDY#, B_PERR#, B_ P AR, B_ GNT#[5:0], B_R EQ #[ 5:0], B_LOCK#, B_P AR64, B_REQ 6 4#, B_SE RR#, B_ STOP# , and B_ TRDY#.
36 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI-X Layo ut Guidelines Figure 17. PCI Clock Distribution and Matching Requireme nts B1499-04 PCI Device 1 PCI Device 2 PCI Device 3 a X0.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 37 PCI-X Layout Guidelines T able 8. PCI-X Clock Layout Requirement s Summary Param e ter Routing Gui delines Signal Group PCI Clocks B_CLKO.
38 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI-X Layo ut Guidelines 8.5 PCI -X T o pology Layo ut Guidelines The PCI-X Addendum to the PC I Local Bus Specifica tion , Revision 1.0b compliant, reco mmends the followin g guideli nes for t he numb er of l oads for you r PCI-X des igns.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 39 PCI-X Layout Guidelines 8.6.1 Embedded PCI-X 133 MHz This section lists the ro uting recommenda tions fo r PCI-X 133 MHz without a slot. Figure 1 8 shows the bl ock diagr am of this t opol o gy and Ta b l e 1 0 descr ibes the ro uting recomm endations.
40 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI-X Layo ut Guidelines 8.6.2 Embedded PCI-X 100 MHz This section lists the embedded routing recommendations for PCI-X 100 MHz. Figur e 19 show s the block di agram of thi s topol ogy and Ta b l e 1 1 descr i bes the rout i ng re com mend atio ns .
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 41 PCI-X Layout Guidelines 8.6.3 PCI-X 66 MHz Embedded T opo logy Figu re 20 and Ta b l e 1 2 provi de routing det ails for a topology w ith an embedded P CI-X 66 MHz application. Figure 20. PCI-X 66 MHz Embedded Routing T opology T able 12.
42 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI-X Layo ut Guidelines 8.6.4 PCI 66 MHz Embedded T opology Figur e 21 an d Ta b l e 1 3 provide routi ng details f or a topolo gy with an embedded PCI 66 MHz design. P Figure 21. PCI 66 MHz Embedded T opology T able 13.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 43 PCI-X Layout Guidelines 8.6.5 PCI 33 MHz Embedded Mode T opolog y Figu re 22 and Ta b l e 1 4 provi de routing det ails for a topology w ith an embedded P CI 33 MHz design. Figure 22. PCI 33 MHz Embedded Mode Routing T opology T able 14.
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Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 45 PCI Express Layout 9 This section provid es an overview of the PC I-Express stackup r ecommended based o n Intel presimulation results.
46 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI Express Layo ut 9.2 PCI-Express Layout Guidelin es The layout guidel ines for PCI-Express were deve loped for an adapter card topologies.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 47 PCI Ex press Layou t Receive Tr ace Length (Card edge finger to 41210 Bridge receiver pin 1.0” min - 6.0” max Length Matching Requirements: T otal allowable intra-pair length mis-m atch must not ex ceed 25 mi ls.
48 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide PCI Express Layo ut This page intentionally le ft blank..
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 49 Circuit Implementations 10 This chapt er describes 4 1210 Bridge circuit implementat ions.
50 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Circuit Implementations 10.1.1 PCI An alog V olt age Filters The following filter circuit is recommended fo r the PCI interface.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 51 Circuit Implementations Figure 24. PCI Express Analog V oltage Filter Circuit Note: . • Place C as close as possible to p ackage pin. • R must be placed between VC C 15 and L. • Route VCCAPE and V SSAPE as diff erential traces.
52 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Circuit Implementations Figure 25. Bandgap Analog V oltage Filter Circuit Note: . • Place C as close as pos sible to package p in. • R must be placed between the 2.5 V supply and L. • Route VCCBGPE and VSSBGPE as differ ential traces.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 53 Circuit Implementations 10.2 Intel® 41210 Serial to Parallel PCI Bridge Referenc e and Comp ensation Pins There are three compensation pins on Intel® 41210 Serial to Parallel PCI Bridge.
54 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Circuit Implementations 10.2.1 SM Bu s The SMBus interface does not have con figuration regist ers. The SMBus address is set by the states of pins SMBUS[5] and SMBUS [3 :1] when PE RST# is asserted as described in Ta b l e 1 7 .
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 55 41210 Bridge Customer Reference Boards 11 This chapt er describes t he 41210 Bridge Custo mer Reference Board (CR B).
56 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide 41210 B ridge Custome r Referenc e Boards 11 . 2 M a t e r i a l The following materials are us ed with the 41210 Brid ge CRB: • FR-4, 0.0 62 in. +/- .0 07, 1.0 oz Copper Power/G ND. • Full len gth PCI Raw C ard (3.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 57 41210 Bridg e Customer Re ference Bo ards 1 1.4 Board Outline Figu re 27 provides the mechanical outline of the 41210 Bridge C RB.
58 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide 41210 B ridge Custome r Referenc e Boards This page intentionally left blank ..
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 59 Design Guide Checklist 12 This checkl ist highlight s design consideratio ns that s hould be review ed prior t o manufacturing an adapter card that implemen ts the 41210 Brid ge prod uct.
60 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Design Guide Checklist T able 20. PCI/PCI-X Interface Signals Signals Recomm endations Reason/Impact X_AD[63:32] X_CB E[7:4]# X_DE VSEL# X.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 61 Design Guide Checklist A_M66E N B_M66E N Controls frequency of the PCI segment when running in conventional PCI mode (33 MHz or 66 MHz): 0 = 33 MHz PCI 1 = 66 MHz PCI • Pull-up using a 8.
62 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Design Guide Checklist T able 21. Miscellaneous Signals Signals Recommend ations Reason/Impact RSTIN# Used for debug purposes. C onnect to VCC33 through an 8.2K Ω pullup resistor for normal operation.
Intel® 412 10 Serial to Pa rallel PCI Bridge Des ign Guide 63 Design Guide Checklist T able 23. Power and Ground Signals Signa l Recommendat ions Reason/Im pa ct RCOM P 100 Ω ±1% (1/4 W) pulldown resistor to ground. The trace impedanc e of this signal sh ould be < 0.
64 Intel® 4121 0 Serial to Parallel PCI Brid ge Design Guide Design Guide Checklist T able 24. JT AG Signals Signal Recomm endations Reason/Impact TCK If not used for JT AG , leave as No Connect Inte.
Un punto importante, dopo l’acquisto del dispositivo (o anche prima di acquisto) è quello di leggere il manuale. Dobbiamo farlo per diversi motivi semplici:
Se non hai ancora comprato il Intel 41210 è un buon momento per familiarizzare con i dati di base del prodotto. Prime consultare le pagine iniziali del manuale d’uso, che si trova al di sopra. Dovresti trovare lì i dati tecnici più importanti del Intel 41210 - in questo modo è possibile verificare se l’apparecchio soddisfa le tue esigenze. Esplorando le pagine segenti del manuali d’uso Intel 41210 imparerai tutte le caratteristiche del prodotto e le informazioni sul suo funzionamento. Le informazioni sul Intel 41210 ti aiuteranno sicuramente a prendere una decisione relativa all’acquisto.
In una situazione in cui hai già il Intel 41210, ma non hai ancora letto il manuale d’uso, dovresti farlo per le ragioni sopra descritte. Saprai quindi se hai correttamente usato le funzioni disponibili, e se hai commesso errori che possono ridurre la durata di vita del Intel 41210.
Tuttavia, uno dei ruoli più importanti per l’utente svolti dal manuale d’uso è quello di aiutare a risolvere i problemi con il Intel 41210. Quasi sempre, ci troverai Troubleshooting, cioè i guasti più frequenti e malfunzionamenti del dispositivo Intel 41210 insieme con le istruzioni su come risolverli. Anche se non si riesci a risolvere il problema, il manuale d’uso ti mostrerà il percorso di ulteriori procedimenti – il contatto con il centro servizio clienti o il servizio più vicino.
