Manuale d’uso / di manutenzione del prodotto CY7C1317CV18 del fabbricante Cypress Semiconductor
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18-Mbit DDR-II SRAM 4-W ord Burst Architecture CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Cypress Semiconductor Corpora tion • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-07161 Rev .
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 2 of 31 Logic Block Diagram (CY7C1317CV18) Logic Block Diagram (CY7C1917CV18) Writ e Reg CLK A (18:0) Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 3 of 31 Logic Block Diagram (CY7C1319CV18) Logic Block Diagram (CY7C1321CV18) Writ e Reg CLK A (19:0) Gen. K K Control Logic Address Register Read Add. Decode Read Data Reg.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 4 of 31 Pin Configuration The pin configuration for CY7C1317CV18, CY7C191 7CV18, CY7C1319CV18, and CY7C1321CV18 follo w .
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 5 of 31 CY7C1319CV18 (1M x 18) 123456789 10 11 A CQ NC/72M A R/W BWS 1 K NC/14 4M LD A NC/36M CQ B NC DQ9.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 6 of 31 Pin Definitions Pin Name IO Pin Descripti on DQ [x:0] Input Output- Synchronous Dat a Input Output S ignals . Inputs are sampled on the rising edge of K and K clocks during valid write operations.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 7 of 31 CQ Output Clock CQ Referenced with Respect to C . This is a free running clock and is synchronized to the input clock for output data (C) of the DDR-II.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 8 of 31 Functional Overview The CY7C1317CV18, CY7C1917CV18, CY7C1 319CV18, and CY7C1321CV18 are synchronous pi pelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and half cycles when DOFF pin is tied HIGH.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 9 of 31 after the read(s), the st ored data from the ear lier write i s writte n into the SRAM array .
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 10 of 31 Application Example Figure 1 shows two DDR-II used in an applicatio n. Figure 1. Application Example T ruth T able The truth table for the CY7C1317CV18, CY7C1917 CV18, CY7C13 19CV18, and CY7C1321CV18 fo llows.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 1 1 of 31 Burst Address T able (CY7C1319CV18, CY7C1321CV18) First Address ( External) Second Addres s (Internal) Third Address (I nternal) Four th Address (Intern al) X.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 12 of 31 Write Cycle Descriptions The write cycle description t able for CY7C1 321CV18 follows.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 13 of 31 IEEE 1 149.1 Serial Boundary Scan (JT AG) These SRAMs incorporate a serial boundary scan T est Access Port (T AP) in the FBGA p ackage. This part is fully comp liant with IEEE S tandard #1 149.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 14 of 31 IDCODE The IDCODE instruction loads a vendor-specific, 32-bi t code into the instruction re gister .
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 15 of 31 T AP Controller St ate Diag ram The state diagram for the T AP controller follows.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 16 of 31 T AP Controller Block Diagram T AP Electrical Characteristics Over the Operating Range [10, 1 1, 12] Parameter Description T est Conditions Min Max Unit V OH1 Output HIGH V oltage I OH = − 2.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 17 of 31 T AP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Ma.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 18 of 31 Identification R egi ster Definitions Instruction Field Va l u e Descriptio n CY7C1317CV18 CY7C1917CV18 CY7 C1319CV18 CY7C1321CV18 Revision Numb er (31:29) 000 000 000 000 V ersion numbe r .
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 19 of 31 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bum p ID 0 6R 28 10G 56 6A 8.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 20 of 31 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be power ed up and initialized in a predefined manner to prevent unde fined operations. Power Up Sequence ■ Apply power and drive DO FF either HIGH or LOW (all other inputs can be HIGH or LOW).
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 21 of 31 Maximum Ratings Exceeding maximum ratin gs may impair the useful life o f the device. These user guidelines are not teste d. S torage T emperature .
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 22 of 31 I DD [19] V DD Operating Supply V DD = Max, I OUT = 0 mA, f = f MAX = 1/t CYC 200 MHz (x8) 580 m.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 23 of 31 Cap acit ance T ested initially and after any design or process change that may affect these parameters. Parameter Description T est Conditions Max Unit C IN Input Capacitance T A = 25 ° C, f = 1 MHz, V DD = 1.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 24 of 31 Switching Characteristics Over the Operating Range [20, 21] Cypress Parameter Consor tium Parame.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 25 of 31 Output T imes t CO t CHQV C/C Clock Rise (or K/K in single clock mode) to Data V alid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns t DOH t CHQX Data Output Hold af ter Output C/C Clock Rise (Active to Active) –0.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 26 of 31 Switching W aveforms Figure 5. Read/Write/Deselect Sequence [2 7, 28, 29 ] K 1 2 3 4 5 6 7 8 9 1.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 27 of 31 Ordering Information Not all of the speed, package and temperature ranges are ava ilable. Please contact your local sales representative or visit www .
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 28 of 31 250 CY7C1317CV18-2 50BZC 51-85180 1 65-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1917CV18-250BZC CY7C1319CV18-250BZC CY7C1321CV18-250BZC CY7C1317CV18-250BZXC 5 1-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 29 of 31 167 CY7C1317CV18-1 67BZC 51-85180 1 65-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial CY7C1917CV18-167BZC CY7C1319CV18-167BZC CY7C1321CV18-167BZC CY7C1317CV18-167BZXC 5 1-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 Document Number: 001-07161 Rev . *D Page 30 of 31 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 A 1 PIN 1 CORNER 15.00±0.10 13.00±0.10 7.00 1.00 Ø0.50 (165X) Ø 0 . 2 5MCAB Ø0.
Document Number: 001-07161 Rev . *D Revised June 18, 2008 Page 31 of 31 QDR RAMs an d Quad Data Rate RAMs comp rise a new family of product s develope d by Cypress, IDT , NEC, Renesas, and Samsung. All pr oduct and co mpany nam es mentioned i n this documen t are the tr ad emarks of their respe ctive hold ers.
Un punto importante, dopo l’acquisto del dispositivo (o anche prima di acquisto) è quello di leggere il manuale. Dobbiamo farlo per diversi motivi semplici:
Se non hai ancora comprato il Cypress Semiconductor CY7C1317CV18 è un buon momento per familiarizzare con i dati di base del prodotto. Prime consultare le pagine iniziali del manuale d’uso, che si trova al di sopra. Dovresti trovare lì i dati tecnici più importanti del Cypress Semiconductor CY7C1317CV18 - in questo modo è possibile verificare se l’apparecchio soddisfa le tue esigenze. Esplorando le pagine segenti del manuali d’uso Cypress Semiconductor CY7C1317CV18 imparerai tutte le caratteristiche del prodotto e le informazioni sul suo funzionamento. Le informazioni sul Cypress Semiconductor CY7C1317CV18 ti aiuteranno sicuramente a prendere una decisione relativa all’acquisto.
In una situazione in cui hai già il Cypress Semiconductor CY7C1317CV18, ma non hai ancora letto il manuale d’uso, dovresti farlo per le ragioni sopra descritte. Saprai quindi se hai correttamente usato le funzioni disponibili, e se hai commesso errori che possono ridurre la durata di vita del Cypress Semiconductor CY7C1317CV18.
Tuttavia, uno dei ruoli più importanti per l’utente svolti dal manuale d’uso è quello di aiutare a risolvere i problemi con il Cypress Semiconductor CY7C1317CV18. Quasi sempre, ci troverai Troubleshooting, cioè i guasti più frequenti e malfunzionamenti del dispositivo Cypress Semiconductor CY7C1317CV18 insieme con le istruzioni su come risolverli. Anche se non si riesci a risolvere il problema, il manuale d’uso ti mostrerà il percorso di ulteriori procedimenti – il contatto con il centro servizio clienti o il servizio più vicino.
